TI-DS90UB921-Q1.pdf资源-CSDN文库

FPD-Link串行器

需积分: 0 15 浏览量 2023-02-01 22:55:44 上传评论 4 收藏 1.74MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源推荐

资源详情

资源评论

R[7:0]

PCLK

PDB

Serializer Deserializer

RGB Display

720p

24-bit color depth

RGB Digital Display Interface

HOST

Graphics

Processor

FPD-Link III

1 Coax / AC Coupled

DS90UB921-Q1 DS90UB922-Q1

PASS

VDDIO

OSS_SEL

SCL

SDA

INTB

I2S AUDIO

(STEREO)

OEN

LOCK

IDx

DAP DAP

G[7:0]

B[7:0]

SCL

SDA

IDx

R[7:0]

PCLK

G[7:0]

B[7:0]

RIN+

RIN-

DOUT+

DOUT-

(1.8V or 3.3V)

(3.3V)

VDDIO

I2S AUDIO

(STEREO)

MODE_SEL

MCLK

PDB

INTB_IN

VDD33

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS488

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

DS90UB921-Q1 具具有有双双向向控控制制通通道道的的 5MHz 到到 96MHz 24 位位彩彩色色 FPD-

Link III 串串行行器器

1 特特性性

• 适用于汽车电子应用

• 具有符合 AEC-Q100 标准的下列结果：

– 器件温度等级 2：-40℃ 至 +105℃ 的环境运行

温度范围

– 器件人体放电模型 (HBM) 静电放电 (ESD) 分类

等级 ±8kV

– 器件组件充电模式 (CDM) ESD 分类等级 C6

• 支持扩展高清 (1920x720p/60Hz) 数字视频格式

• 支持 5MHz–96MHz 像素时钟 (PCLK)（STP 模

式）

• 支持 15MHz–96MHz PCLK（同轴模式）

• RGB888 + VS、HS 和 DE

• 并行 LVCMOS 视频输入

• 允许存在幅值偏差的扩频输入

• 4 条可选的双向 GPIO 通道

• 双向控制接口通道接口，可连接到 I

C 兼容串行控

制总线

• 可选的 I

S 支持

• 长达 10 米的交流耦合同轴或屏蔽双绞线 (STP) 互

连

• 通过 1.8V 或 3.3V 兼容 LVCMOS I/O 接口实现

3.3V 单电源运行

• 具有嵌入式时钟的直流均衡和扰频数据

• 内部模式生成

• 低功率模式最大限度地减少了功率耗散

• >8kV ISO 10605 静电放电 (ESD) 额定值

2 应应用用

• 汽车用触摸显示屏

• 汽车导航显示屏

• 汽车仪表板

3 说说明明

DS90UB921-Q1 串行器与 DS90UB922-Q1、

DS90UB926Q-Q1、DS90UB928Q-Q1、DS90UB948-

Q1 或 DS90UB940-Q1 解串器配套使用，可提供完整

的数字接口以实现汽车显示屏和图像传感应用中视频、

音频和控制数据的高速并行传输。

该芯片组非常适合 WVGA 和 HD 格式的车载视频显示

系统。DS90UB921-Q1 整合了嵌入式双向控制通道和

低延迟 GPIO 控制。该芯片组将并行接口转换为单对

高速串行化接口。FPD-Link III 串行总线方案支持通过

单个链路实现高速视频数据传输和双向控制通信的全双

工控制。通过单个差分对（或单线）整合视频数据和控

制可减少互连线尺寸和重量，同时还消除了偏差问题并

简化了系统设计。

DS90UB921-Q1 串行器内嵌时钟，可通过直流扰频 &

均衡数据有效载荷，并将信号电平转换为高速低压差分

（或单端）信令。最多有 24 个数据位可随视频控制信

号一同串行化。

低压摆幅信令的使用、数据换序和随机生成以及扩频定

时兼容性最大限度地减少了电磁干扰 (EMI)。

来自下行解串器的远程中断被映射至一个本地输出引

脚。

器器件件信信息息

(1)

部部件件号号封封装装封封装装尺尺寸寸（（标标称称值值））

DS90UB921-Q1 WQFN (48) 7.00mm x 7.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 6

6.1 Absolute Maximum Ratings ..................................... 6

6.2 ESD Ratings - JEDEC ............................................. 6

6.3 ESD Ratings—IEC and ISO...................................... 6

6.4 Recommended Operating Conditions....................... 6

6.5 Thermal Information.................................................. 7

6.6 DC Electrical Characteristics .................................... 7

6.7 AC Electrical Characteristics..................................... 9

6.8 PCLK Timing Requirements ..................................... 9

6.9 Recommended Timing for the Serial Control Bus .. 10

6.10 Switching Characteristics...................................... 13

6.11 Typical Charateristics ........................................... 14

7 Detailed Description............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 15

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 24

7.5 Programming .......................................................... 27

7.6 Register Maps ........................................................ 28

8 Application and Implementation ........................ 40

8.1 Application Information............................................ 40

8.2 AVMUTE Operation ................................................ 40

8.3 Typical Application .................................................. 41

9 Power Supply Recommendations...................... 45

9.1 Power Up Requirements and PDB Pin................... 45

9.2 CML Interconnect Guidelines.................................. 46

10 Layout................................................................... 47

10.1 Layout Guidelines ................................................. 47

10.2 Layout Example .................................................... 48

11 器器件件和和文文档档支支持持 ..................................................... 51

11.1 文档支持................................................................ 51

11.2 社区资源................................................................ 51

11.3 商标 ....................................................................... 51

11.4 静电放电警告......................................................... 51

11.5 Glossary................................................................ 51

12 机机械械、、封封装装和和可可订订购购信信息息....................................... 51

4 修修订订历历史史记记录录

日日期期修修订订版版本本注注释释

2016 年 3 月 * 最初发布版本。

DS90UB921-Q1

ZHCSEV0 –MARCH 2016

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NUMBER

HS 3 I, LVCMOS,

Horizontal Sync Input Pin

Video control signal pulse width must be 3 PCLKs or longer to be transmitted when

the Control Signal Filter is enabled. There is no restriction on the minimum transition

pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions

per 130 PCLKs.

See Video Control Signal Filter.

VS 4 I, LVCMOS,

Vertical Sync Input Pin

Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse

width is 130 PCLKs.

See Video Control Signal Filter.

DE 5 I, LVCMOS,

Data Enable Input Pin

Video control signal pulse width must be 3 PCLKs or longer to be transmitted when

the Control Signal Filter is enabled. There is no restriction on the minimum transition

pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions

per 130 PCLKs.

See Video Control Signal Filter.

PCLK 10 I, LVCMOS,

Pixel Clock Input Pin. Strobe edge set by TRFB configuration register. See 表 7

0x03[0].

I2S_CLK,

I2S_WC,

I2S_DA

13, 12, 11 Multi-function

I, LVCMOS,

Digital Audio Interface Data Input Pins

Leave open if unused

I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as

GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.

OPTIONAL PARALLEL INTERFACE - Layout note: for unused interface pins, tie to an external pulldown

GPIO[3:0] 36, 35, 26, 25 Multi-function

I/O, LVCMOS,

General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin

or configuration register. See 表 7 0x0D - 0x0F.

Leave open if unused.

Shared with DIN9, DIN8, DIN1 and DIN0

GPO_REG[

7:4]

12, 11, 44, 43 Multi-function

O, LVCMOS,

General Purpose Outputs and set by configuration register. See 表 7 0x0F - 0x11.

Share with I2S_WC, I2S_DA, or DIN17, DIN16.

CONTROL

PDB 21 I, LVCMOS,

Power-down Mode Input Pin

PDB = H, device is enabled (normal operation)

Refer to Power Up Requirements and PDB Pin section.

PDB = L, device is powered down.

When the device is in the powered down state, the Driver Outputs are both HIGH, the

PLL is shutdown, and IDD is minimized. Control Registers are RESET.

MODE_SEL 24 S Device Configuration Select. See 表 5.

FSEL 15 I, LVCMOS,

Frequency Mode Select. Enables Intermediate Frequency mode for coaxial operation.

See Frequency Mode Optimizations.

IDx 6 S I

C Serial Control Bus Device ID Address Select

External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.

Connect to external pull-up and pull-down resistor to create a voltage divider. See 表

SCL 8 I/O, Open

Drain

C Clock Input / Output Interface

Must have an external pull-up to VDD33, DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.

SDA 9 I/O, Open

Drain

C Data Input / Output Interface

Must have an external pull-up to VDD33, DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.

DS90UB921-Q1

www.ti.com.cn

ZHCSEV0 –MARCH 2016

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NUMBER

(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.

STATUS - Layout note: for unused interface pins, leave as No Connect

INTB 31 O, Open Drain Interrupt

INTB = H, normal

INTB = L, Interrupt request

Typically connected with 4.7kΩ to VDDIO.

REM_INTB 16 O, LVCMOS,

Interrupt. Mirrors status of INTB_IN from the remote deserializer. Note: REM_INTB

will be driven LOW until lock is achieved with the downstream deserializer.

REM_INTB = H, normal

REM_INTB = L, interrupt request

FPD-LINK III SERIAL INTERFACE

DOUT+ 20 O, LVDS True Output

The output must be AC-coupled per the typical connection diagram.

DOUT- 19 O, LVDS Inverting Output

The output must be AC-coupled per the typical connection diagram.

CMF 23 CAP Common Mode Filter.

Typically connected with 0.1µF to GND

POWER AND GROUND

(1)

VDD33 22 Power Power to on-chip regulator 3.0 V - 3.6 V. Typically connected with 4.7 uF to GND

VDDIO 30 Power LVCMOS I/O Power 1.71 V - 1.89 V OR 3.0 V - 3.6 V. Typically connected with 4.7

uF to GND

GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN

package. Connect to the ground plane (GND) with at least 9 vias.

REGULATOR CAPACITOR

CAPHS12,

CAPP12

17, 14 CAP Decoupling capacitor connection for on-chip regulator. Typically connected with 4.7uF

to GND at each CAP pin.

CAPL12 7 CAP Decoupling capacitor connection for on-chip regulator. Typically connected with two

4.7uF to GND at this CAP pin.

OTHERS

RES1 18 GND Reserved. Tie to Ground.

The definitions below define the functionality of the I/O cells for each pin. I/O TYPE:

• CAP = Capacitor connection

• LVCMOS = LVCMOS pin; Referenced to VDDIO IO supply

• I = Input

• O = Output

• I/O = Input/Output

• S = Strap pin. All strap pins have weak internal pull-ups or pull-downs. If the default strap value is needed to

be changed then an external resistor should be used.

• PD, PU = Weak Internal Pull-Down/Pull-Up

• Multi-function pin

剩余54页未读，继续阅读

评论收藏

内容反馈

不觉明了

粉丝: 834
资源: 4209

会员权益专享

TI-DS90UB921-Q1.pdf

TI-DS90UB913A-Q1.pdf

TI-DS90UB913Q-Q1.pdf

TI-DS90UB925Q-Q1.pdf

TI-DS90UB947N-Q1.pdf

TI-DS90UB949A-Q1.pdf

TI-DS90UB927Q-Q1.pdf

TI-DS90UB926Q-Q1.pdf

TI-DS90UB904Q-Q1.pdf

TI-DS90UB928Q-Q1.pdf

TI-DS90UB902Q-Q1.pdf

TI-DS90UB914A-Q1.pdf

TI-DS90UB929-Q1.pdf

TI-DS90UB947-Q1.pdf

TI-DS90UB924-Q1.pdf

TI-DS90UB949-Q1.pdf

TI-DS90UB935-Q1.pdf

TI-DS90UB933-Q1.pdf

TI-DS90UB953-Q1.pdf

TI-DS90UB953A-Q1.pdf

ChatGPT使用总结：150个ChatGPT提示词模板（完整版）

哈尔滨工业大学-ChatGPT调研报告-2023.3.6-94页.pdf

如何在New Bing中免费体验ChatGPT4.0

分享几款免费chatGPT国内镜像.zip

249个 ChatGPT 关键词汇总 中文版

11个国内免费可用的ChatGPT网站.zip

it项目启动阶段 会议决议表（合集）.doc

会员权益专享

最新资源

249个 ChatGPT 关键词汇总中文版

it项目启动阶段会议决议表（合集）.doc