TI-DS90UB924-Q1.pdf资源-CSDN文库

FPD-Link串行器

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100Q STP Cable

LVDS Display

720p or

Graphic

Proccesor

DS90UB924-Q1

Deserializer

FPD-Link III

1 Pair/AC Coupled

FPD-Link

(Open LDI)

TxOUT1+/-

TxCLKOUT+/-

TxOUT2+/-

TxOUT0+/-

TxOUT3+/-

DDIO

(1.8V or 3.3V)

RIN+

RIN-

SDA

SCL

I2S

MCLK

DD33

(3.3V)

MODE_SEL

BISTEN

LFMODE

MAPSEL

PDB

OSS_SEL

OEN

LOCK

PASS

INTB_IN

IDx

R[7:0]

PCLK

PDB

Serializer

RGB Digital Display Interface

HOST

Graphics

Processor

DS90UB921-Q1

DDIO

SCL

SDA

I2S AUDIO

(STEREO)

IDx

DAP

G[7:0]

B[7:0]

DOUT+

DOUT-

(1.8V or 3.3V)

(3.3V)

DD33

INTB

MODE_SEL

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

Reference

Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNLS512

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

DS90UB924-Q1 具具有有双双向向控控制制通通道道的的 5MHz 至至 96MHz 24 位位彩彩色色 FPD-

Link III 转转 OpenLDI 解解串串器器

1 特特性性

• 适用于汽车电子应用 AEC-Q100

– 器件温度 2 级：-40℃ 至 +105℃ 的环境运行温

度范围

– 器件人体放电模型 (HBM) 静电放电 (ESD) 分类

等级 ±8kV

– 带电器件模型 (CDM) ESD 分类等级 C6

• 支持 5MHz 至 96MHz 像素时钟

• 双向控制通道接口，可连接兼容 I

C 的串行控制总

线

• 低电磁干扰 (EMI) OpenLDI 视频输出

• 支持高清 (720p) 数字视频

• 支持 RGB888 + VS，HS，DE 和 I2S 音频

• 多达 4 个适用于环绕立体声应用的 I2S 数字音频

输出

• 4 条具有 2 个专用引脚的双向通用输入输出 (GPIO)

通道

• 通过兼容 1.8V 或 3.3V 的低电压互补金属氧化物半

导体 (LVCMOS) I/O 接口实现 3.3V 单电源供电运

行

• 具有嵌入式时钟的直流均衡和扰频数据

• 自适应电缆均衡

• 内部模式生成

• 向后兼容模式

2 应应用用范范围围

• 汽车用触摸显示屏

• 汽车导航显示屏

• 汽车仪表板

3 说说明明

DS90UB924-Q1 解串器与 DS90UB921-Q1、

DS90UB925Q-Q1、DS90UB927Q-Q1、DS90UB929-

Q1、DS90UB949-Q1 或 DS90UB947-Q1 串行器配套

使用，可针对汽车信息娱乐系统内的数字视频和音频的

分配提供一套解决方案。该器件可将嵌入时钟的高速串

行化接口（通过单信号对 (FPD-Link III) 传输）转换为

四个 LVDS 数据/控制流、一个 LVDS 时钟对

(OpenLDI) 以及 I2S 音频数据。FPD-Link III 串行总线

方案支持通过单条差分链路实现高速正向通道数据传输

和低速反向通道通信的全双工控制。通过单个差分对整

合音频、视频和和控制数据可减小互连线尺寸和重量，

同时还消除了偏差问题并简化了系统设计。

通过对串行输入数据流使用自适应输入均衡功能，可对

传输介质损耗和确定性抖动进行补偿。通过使用低压差

分信令可最大限度减少电磁干扰 (EMI)。

器器件件信信息息

(1)

部部件件号号封封装装封封装装尺尺寸寸（（标标称称值值））

DS90UB924-Q1 WQFN (48) 7.00mm x 7.00mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用范范围围................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 6

6.1 Absolute Maximum Ratings ..................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 DC Electrical Characteristics .................................... 7

6.6 AC Electrical Characteristics..................................... 9

6.7 DC and AC Serial Control Bus Characteristics....... 10

6.8 Timing Requirements for the Serial Control Bus .... 10

6.9 Timing Requirements.............................................. 11

6.10 Typical Characteristics.......................................... 15

7 Detailed Description............................................ 16

7.1 Overview ................................................................. 16

7.2 Functional Block Diagram ....................................... 16

7.3 Feature Description................................................. 17

7.4 Device Functional Modes........................................ 27

7.5 Programming........................................................... 33

7.6 Register Maps......................................................... 35

8 Application and Implementation ........................ 50

8.1 Application Information............................................ 50

8.2 Typical Application .................................................. 50

9 Power Supply Recommendations...................... 53

9.1 Power Up Requirements and PDB Pin................... 53

9.2 Analog Power Signal Routing ................................. 55

10 Layout................................................................... 55

10.1 Layout Guidelines ................................................. 55

10.2 Layout Example .................................................... 57

11 器器件件和和文文档档支支持持 ..................................................... 58

11.1 文档支持................................................................ 58

11.2 社区资源................................................................ 58

11.3 商标 ....................................................................... 58

11.4 静电放电警告......................................................... 58

11.5 Glossary................................................................ 58

12 机机械械、、封封装装和和可可订订购购信信息息....................................... 58

4 修修订订历历史史记记录录

日日期期修修订订版版本本注注释释

2016 年 4 月 * 首次发布。

DS90UB924-Q1

ZHCSEY4 –APRIL 2016

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NO.

GPIO_REG[8

:5]

8, 10, 7, 3 I/O, LVCMOS

with pulldown

General Purpose I/O, register access only

Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB

I2S_DA

I2S_DB

I2S_DC

I2S_DD

O, LVCMOS Digital Audio Interface I2S Data Outputs

Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3

INTB_IN 43 I, LVCMOS

with pulldown

Interrupt Input

Shared with BISTC

MCLK

I2S_WC

I2S_CLK

O, LVCMOS Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs

I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8

SDOUT

SWC

O, LVCMOS

with pulldown

Auxiliary Digital Audio Interface I2S Data Output and Word Clock

Shared with GPIO1 and GPIO0

CONTROL AND CONFIGURATION

BISTC 43 I, LVCMOS

with pulldown

BIST Clock Select

Shared with INTB_IN

Requires a 10-KΩ pullup if set HIGH

BISTEN 9 I, LVCMOS

with pulldown

BIST Enable

Requires a 10-KΩ pullup if set HIGH

IDx 12 I, Analog I2C Address Select

External pullup to VDD33 is required under all conditions. DO NOT FLOAT.

Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.

See Table 7

LFMODE 32 I, LVCMOS

with pulldown

Low Frequency Mode Select

LFMODE = 0, 15-MHz ≤ TxCLKOUT ≤ 96-MHz (Default)

LFMODE = 1, 5-MHz ≤ TxCLKOUT < 15-MHz

Requires a 10-KΩ pullup if set HIGH

MAPSEL 26 I, LVCMOS

with pulldown

FPD-Link (OpenLDI) Output Map Select

MAPSEL = 0, LSBs on TxOUT3± (Default)

MAPSEL = 1, MSBs on TxOUT3±

Requires a 10-KΩ pullup if set HIGH

MODE_SEL 48 I, Analog Device Configuration Select

Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4 channel (I2S_B),

and Long Cable (LCBL) modes

Connect to external pullup to VDD33 and pulldown to GND resistors to create a voltage

divider. DO NOT FLOAT

See Table 6

OEN 30 I, LVCMOS

with pulldown

Output Enable

Requires a 10-KΩ pullup if set HIGH

See Table 5

OSS_SEL 35 I, LVCMOS

with pulldown

Output Sleep State Select

Requires a 10 KΩ pullup if set HIGH

See Table 5

PDB 1 I, LVCMOS Power-down Mode Input Pin

Must be driven or pulled up to VDD33. Refer to Power Up Requirements and PDB PinPower

Up Requirements and PDB Pin in Application and Implementation.

PDB = H, device is enabled (normal operation)

PDB = L, device is powered down

When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state,

the PLL is shutdown, and I

is minimized. Control Registers are RESET.

SCL 5 I/O, Open

Drain

C Clock Input/Output Interface

Must have an external pullup to V

DD33

. DO NOT FLOAT

Recommended pullup: 4.7 KΩ

SDA 4 I/O, Open

Drain

I2C Data Input/Output Interface

Must have an external pullup to VDD33. DO NOT FLOAT

Recommended pullup: 4.7 kΩ

剩余64页未读，继续阅读

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