2
DS90UB933-Q1
ZHCSFV6C –AUGUST 2016–REVISED NOVEMBER 2019
www.ti.com.cn
版权 © 2016–2019, Texas Instruments Incorporated
目目录录
1 特特性性.......................................................................... 1
2 应应用用.......................................................................... 1
3 说说明明.......................................................................... 1
4 修修订订历历史史记记录录 ........................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Recommended Serializer Timing For PCLK............. 9
6.7 AC Timing Specifications (SCL, SDA) - I2C-
Compatible............................................................... 10
6.8 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C-Compatible ................................. 10
6.9 Serializer Switching Characteristics........................ 11
6.10 Timing Diagrams................................................... 12
6.11 Typical Characteristics.......................................... 14
7 Detailed Description............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ...................................... 15
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 19
7.5 Programming .......................................................... 24
7.6 Register Maps......................................................... 28
8 Application and Implementation ........................ 35
8.1 Application Information............................................ 35
8.2 Typical Applications ................................................ 37
9 Power Supply Recommendations...................... 40
10 Layout................................................................... 41
10.1 Layout Guidelines ................................................. 41
10.2 Layout Example .................................................... 42
11 器器件件和和文文档档支支持持 ..................................................... 44
11.1 文档支持................................................................ 44
11.2 接收文档更新通知 ................................................. 44
11.3 社区资源................................................................ 44
11.4 商标 ....................................................................... 44
11.5 静电放电警告......................................................... 44
11.6 Glossary................................................................ 44
12 机机械械、、封封装装和和可可订订购购信信息息....................................... 44
4 修修订订历历史史记记录录
Changes from Revision B (September 2018) to Revision C Page
• Added register 0x27[5] to register map ............................................................................................................................... 33
Changes from Revision A (December 2016) to Revision B Page
• Added recommendation to ensure GPO2 is low when PDB goes high ................................................................................. 4
• Added external clock input frequency range ......................................................................................................................... 6
• Added strap pin input current specification for MODE and IDX pins .................................................................................... 6
• Updated T
JIT1
PCLK input jitter in the external oscillator mode.............................................................................................. 9
• Added that 0.45UI T
JIT2
maximum is when used with DS90UB934-Q1 and added new foot note ....................................... 9
• Added clarification on MODE pin description in PCLK from imager mode ......................................................................... 20
• Updated the MODE setting values to ratio from voltage ...................................................................................................... 21
• Updated IDX setting values to ratio from voltage................................................................................................................. 26
• Added register "TYPE" column per legend ......................................................................................................................... 28
• Added type and default value to the reserved register bits that were missing this information ........................................... 28
• Added that register 0x00[7:1] does not auto update IDX strapped address ....................................................................... 28
• Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b) ................................................................ 30
• Added reference to Power over Coax Application report ..................................................................................................... 35
• Clarified description on PDB pin usage during power up .................................................................................................... 35
• Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high ............................... 35
• Added GPO2 to suggested power-up sequencing diagram ................................................................................................ 35
• Added timing constraint for PDB to GPO2 delay ................................................................................................................ 36
• Revised coax connection diagram to include pulldown resistor for GPO2 ......................................................................... 37
• Revised STP connection diagram to include pulldown resistor for GPO2 .......................................................................... 39
