TI-DS90UB947-Q1.pdf_DS90UB947TRGCRQ1资源-CSDN文库

FPD-Link串行器

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FPD-Link III

2 lanes @3Gbps / per

Lane

VDDIO

1.8V

IDx

DOUT0+

DOUT0-

1.1V

DOUT1+

DOUT1-

RIN0+

RIN0-

RIN1+

RIN1-

CLK+/-

CLK2+/-

FPD-Link

(OpenLDI)

D0+/-

D1+/-

D2+/-

D3+/-

D4+/-

D5+/-

D6+/-

D7+/-

DS90UB947-Q1

Serializer

DS90UB948-Q1

Deserializer

IDx

D_GPIO

(SPI)

D_GPIO

(SPI)

LVDS

Display

1080p60

or Graphic

Processor

Graphics

Processor

I2C

VDDIO

1.8V or 3.3V

1.2V

I2C

3.3V1.8V

CLK+/-

D0+/-

D1+/-

D2+/-

D3+/-

D4+/-

D5+/-

D6+/-

D7+/-

FPD-Link

(OpenLDI)

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS454

DS90UB947-Q1

ZHCSD36A –NOVEMBER 2014–REVISED MARCH 2019

DS90UB947-Q1 1080p OpenLDI 到到 FPD-Link III 串串行行器器

1 特特性性

• 符合面向汽车应用的 AEC-Q100 标准

– 器件温度等级 2：–40°C 至 +105°C，T

• 支持高达 170 MHz 的时钟频率，可实现 WUXGA

(1920x1200) 和 1080p60 分辨率和 24 位色深

• 单路和双路 FPD-Link III 输出

– 单链路：高达 96MHz 的像素时钟

– 双链路：高达 170MHz 的像素时钟

• 单通道和双通道 OpenLDI (LVDS) 接收器

– 可配置的 18 位 RGB 或 24 位 RGB

• 高速反向通道，支持高达 2Mbps 的 GPIO

• 具有自动温度和老化补偿功能，支持长达 15 米的

电缆

• 具有 1Mbps 快速模式增强版的 I2C（主/从）

• SPI 直通接口

• 向后兼容 DS90UB926Q-Q1 和 DS90UB928Q-Q1

FPD-Link III 解串器

2 应应用用

• 汽车信息娱乐：

– 车载信息娱乐 (IVI) 主机和人机交互界面 (HMI)

模块

– 后座娱乐系统

– 数字仪表组

• 安全和监控摄像头

3 说说明明

DS90UB947-Q1 是一款 OpenLDI 到 FPD-Link III 桥

接器件，与 FPD-Link IIIDS90UB940-Q1/DS90UB948-

Q1解串器配合使用，可通过经济高效的 50Ω 单端同轴

电缆或 100Ω 差分屏蔽双绞线 (STP) 电缆提供单通道

或双通道高速串行流。它对 OpenLDI 输入进行串行化

处理，支持高达 WUXGA 和 1080p60 的视频分辨率

（24 位色深）。

FPD-Link III 接口支持通过同一条差分链路进行视频和

音频数据传输以及全双工控制（包括 I2C 和 SPI 通

信）。通过两个差分对实现视频数据和控制的整合可减

小互连线尺寸和重量，并简化系统设计。通过使用低压

差分信令、数据换序和随机生成更大限度地减少了电磁

干扰 (EMI)。在向后兼容模式下，该器件在单一差分链

路上最高可支持 WXGA 和 720p 分辨率（24 位色

深）。

DS90UB947-Q1 支持通过外部 I2S 接口接收多通道音

频。该器件接收的音频数据会被加密并通过 FPD-Link

III 接口发送出去，之后再由解串器重新生成。

器器件件信信息息

(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

DS90UB947-Q1 VQFN (64) 9.00mm x 9.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

应应用用图图

DS90UB947-Q1

ZHCSD36A –NOVEMBER 2014–REVISED MARCH 2019

www.ti.com.cn

目目录录

1 特特性性.......................................................................... 1

2 应应用用.......................................................................... 1

3 说说明明.......................................................................... 1

4 修修订订历历史史记记录录 ........................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 6

6.1 Absolute Maximum Ratings ..................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 DC Electrical Characteristics .................................... 7

6.6 AC Electrical Characteristics..................................... 9

6.7 DC and AC Serial Control Bus Characteristics....... 10

6.8 Recommended Timing for the Serial Control Bus .. 10

6.9 Timing Diagrams..................................................... 11

6.10 Typical Characteristics.......................................... 14

7 Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 15

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 32

7.5 Programming........................................................... 34

7.6 Register Maps......................................................... 38

8 Application and Implementation ........................ 67

8.1 Applications Information.......................................... 67

8.2 Typical Applications ................................................ 67

9 Power Supply Recommendations...................... 72

9.1 Power-Up Requirements and PDB Pin................... 72

10 Layout................................................................... 73

10.1 Layout Guidelines ................................................. 73

10.2 Layout Example .................................................... 74

11 器器件件和和文文档档支支持持 ..................................................... 75

11.1 文档支持 ............................................................... 75

11.2 商标 ....................................................................... 75

11.3 静电放电警告......................................................... 75

11.4 术语表 ................................................................... 75

12 机机械械、、封封装装和和可可订订购购信信息息....................................... 75

4 修修订订历历史史记记录录

Changes from Original (November 2014) to Revision A Page

• Added T

CLH1/2

and T

CHL1/2

parameters to the Recommended Operating Conditions table..................................................... 6

• Change I

TJIT

specification from min to max and added test conditions to the AC Electrical Characteristics table ................ 9

• Removed t

PLD

Max specification in the AC Electrical Characteristics table............................................................................ 9

• Added additional HSCC information to the SPI Mode Configuration section....................................................................... 22

• Changed register information about GPIO0 modes x00 and x10 ........................................................................................ 42

• Changed register information about GPIO1 modes x00 and x10 ........................................................................................ 43

• Added registers 0x40, 0x41, 0x42........................................................................................................................................ 52

• Changed register 0x4F[7] information .................................................................................................................................. 53

• Changed register 0x4F[5] information .................................................................................................................................. 53

• Added page 0x10 registers................................................................................................................................................... 66

• Added information to Power-Up Requirements and PDB Pin section.................................................................................. 72

DS90UB947-Q1

ZHCSD36A –NOVEMBER 2014–REVISED MARCH 2019

www.ti.com.cn

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NO.

CLK+ 58 I, LVDS True LVDS Clock Input

Each pair requires external 100-Ω differential termination for standard LVDS levels

LFOLDI 63 Analog OpenLDI Loop Filter

Connect to a 10-nF capacitor to GND

FPD-LINK III SERIAL PINS

DOUT0- 26 I/O FPD-Link III Inverting Output 0

The output must be coupled with a 33-nF capacitor

DOUT0+ 27 I/O FPD-Link III True Output 0

The output must be coupled with a 33-nF capacitor

DOUT1- 22 I/O FPD-Link III Inverting Output 1

The output must be coupled with a 33-nF capacitor

DOUT1+ 23 I/O FPD-Link III True Output 1

The output must be coupled with a 33-nF capacitor

LF 20 Analog FPD-Link III Loop Filter

Connect to a 10-nF capacitor to GND

CONTROL PINS

SDA 48 IO, Open-Drain I2C Data Input / Output Interface

Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. DO NOT FLOAT.

Recommended pullup: 4.7 kΩ.

SCL 47 IO, Open-Drain I2C Clock Input / Output Interface

Open-drain. Must have an external pullup resistor to 1.8 V or 3.3 V. DO NOT FLOAT.

Recommended pullup: 4.7 kΩ.

I2CSEL 13 I, LVCMOS I2C Voltage Level Strap Option

Tie to V

DDIO

with a 10-kΩ resistor for 1.8-V I2C operation.

Leave floating for 3.3-V I2C operation.

This pin is read as an input at power up.

IDx 19 I, Analog I2C Address Select

External pullup to VDD18 is required under all conditions. DO NOT FLOAT.

Connect to external pullup and pulldown resistors to create a voltage divider.

MODE_SEL0 18 Analog Mode Select 0 Input. Refer to Table 7.

MODE_SEL1 32 Analog Mode Select 1 Input. Refer to Table 8.

PDB 31 I, LVCMOS Power-Down Mode Input Pin

INTB 49 O, Open-Drain Remote interrupt

INTB = H, Normal Operation

INTB = L, Interrupt Request

Recommended pullup: 4.7 kΩ to V

DDIO

. DO NOT FLOAT.

REM_INTB 10 O, LVCMOS LVCMOS Output

REM_INTB will directly mirror the status of the INTB_IN signal from the remote device. No

separate serializer register read will be required to reset and change the status of this pin.

SPI PINS

MOSI 46 IO, LVCMOS SPI Master Output Slave Input

Only available in Dual Link Mode. Shared with D_GPIO0

MISO 45 IO, LVCMOS SPI Master Input Slave Output

Only available in Dual Link Mode. Shared with D_GPIO1

SPLK 44 IO, LVCMOS SPI Clock

Only available in Dual Link Mode. Shared with D_GPIO2

SS 43 IO, LVCMOS SPI Slave Select

Only available in Dual Link Mode. Shared with D_GPIO3

HIGH-SPEED GPIO PINS

D_GPIO0 46 IO, LVCMOS High-Speed GPIO0

Only available in Dual Link Mode. Shared with MOSI

D_GPIO1 45 IO, LVCMOS High-Speed GPIO1

Only available in Dual Link Mode. Shared with MISO

D_GPIO2 44 IO, LVCMOS High-Speed GPIO2

Only available in Dual Link Mode. Shared with SPLK

DS90UB947-Q1

www.ti.com.cn

ZHCSD36A –NOVEMBER 2014–REVISED MARCH 2019

Pin Functions (continued)

I/O, TYPE DESCRIPTION

NAME NO.

D_GPIO3 43 IO, LVCMOS High-Speed GPIO3

Only available in Dual Link Mode. Shared with SS

GPIO PINS

GPIO0 14 IO, LVCMOS General-Purpose Input/Output 0

GPIO1 15 IO, LVCMOS General-Purpose Input/Output 1

GPIO2 38 IO, LVCMOS General-Purpose Input/Output 2

Shared with I2S_DC

GPIO3 39 IO, LVCMOS General-Purpose Input/Output 3

Shared with I2S_DD

GPIO5_REG 37 IO, LVCMOS General-Purpose Input/Output 5

Local register control only. Shared with I2S_DB

GPIO6_REG 36 IO, LVCMOS General-Purpose Input/Output 6

Local register control only. Shared with I2S_DA

GPIO7_REG 34 IO, LVCMOS General-Purpose Input/Output 7

Local register control only. Shared with I2S_WC

GPIO8_REG 35 IO, LVCMOS General-Purpose Input/Output 8

Local register control only. Shared with I2S_CLK

SLAVE MODE LOCAL I2S CHANNEL PINS

I2S_WC 34 I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG

I2S_CLK 35 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG

I2S_DA 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG

I2S_DB 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG

I2S_DC 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2

I2S_DD 39 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3

POWER AND GROUND PINS

VDD18 24

Power 1.8-V (±5%) supply. Refer to Figure 35 or Figure 36.

VDDOA11 50

Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.

VDDA11 12 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.

VDDHS11 21

Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.

VDDL11 9

Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.

VDDOP11 61 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.

VDDP11 17 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.

VDDS11 25 Power 1.1-V (±5%) supply. Refer to Figure 35 or Figure 36.

VDDIO 16

Power 1.8-V (±5%) LVCMOS I/O Power. Refer to Figure 35 or Figure 36.

GND Thermal

Pad

Ground.

OTHER PINS

RES0

RES2

RES3

Reserved. Tie to GND.

RES1 30 Reserved. Connect with 50Ω to GND.

NC 11 No connect. Leave floating Do not connect to VDD or GND.

剩余83页未读，继续阅读

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