TI-DS90UB947N-Q1.pdf

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS90UB947N-Q1 VQFN (64) 9.00 mm × 9.00 mm

(1) For all available packages, see the orderable addendum at

2

6.1 Absolute Maximum Ratings ..................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 DC Electrical Characteristics .................................... 7

6.6 AC Electrical Characteristics..................................... 8

6.7 DC and AC Serial Control Bus Characteristics......... 9

D7-

D6-

D5-

D4-

D3-

7

5

3

1

I, LVDS Inverting LVDS Data Inputs

Each pair requires external 100-Ω differential termination for standard LVDS levels

D4+

D3+

D2+

D1+

D0+

2

CLK- 57 I, LVDS Inverting LVDS Clock Input

Each pair requires external 100-Ω differential termination for standard LVDS levels

4

DOUT0- 26 I/O FPD-Link III Inverting Output 0

The output must be coupled with a 100-nF or 33-nF capacitor

DOUT0+ 27 I/O FPD-Link III True Output 0

The output must be coupled with a 100-nF or 33-nF capacitor

DOUT1- 22 I/O FPD-Link III Inverting Output 1

The output must be coupled with a 100-nF or 33-nF capacitor

DOUT1+ 23 I/O FPD-Link III True Output 1

The output must be coupled with a 100-nF or 33-nF capacitor

LF 20 Analog FPD-Link III Loop Filter

Connect to a 10-nF capacitor to GND

Recommended pullup: 4.7 kΩ.

I2CSEL 13 I, LVCMOS I2C Voltage Level Strap Option

Tie to V

Leave floating for 3.3-V I2C operation.

This pin is read as an input at power up.

IDx 19 I, Analog I2C Address Select

Connect to external pullup and pulldown resistors to create a voltage divider.

MODE_SEL0 18 Analog Mode Select 0 Input. Refer to Table 7.

REM_INTB 10 O, LVCMOS LVCMOS Output

REM_INTB will directly mirror the status of the INTB_IN signal from the remote device. No

separate serializer register read will be required to reset and change the status of this pin.

MOSI 46 IO, LVCMOS SPI Master Output Slave Input

Only available in Dual Link Mode. Shared with D_GPIO0

MISO 45 IO, LVCMOS SPI Master Input Slave Output

Only available in Dual Link Mode. Shared with D_GPIO1

SPLK 44 IO, LVCMOS SPI Clock

Only available in Dual Link Mode. Shared with D_GPIO2

SS 43 IO, LVCMOS SPI Slave Select

Only available in Dual Link Mode. Shared with D_GPIO3

GPIO0 14 IO, LVCMOS General-Purpose Input/Output 0

GPIO1 15 IO, LVCMOS General-Purpose Input/Output 1

GPIO2 38 IO, LVCMOS General-Purpose Input/Output 2

Shared with I2S_DC

GPIO3 39 IO, LVCMOS General-Purpose Input/Output 3

Shared with I2S_DD

GPIO5_REG 37 IO, LVCMOS General-Purpose Input/Output 5

Local register control only. Shared with I2S_DB

GPIO6_REG 36 IO, LVCMOS General-Purpose Input/Output 6

Local register control only. Shared with I2S_DA

I2S_CLK 35 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG

I2S_DA 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG

I2S_DB 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG

I2S_DC 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2

I2S_DD 39 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3

VDD18 24

VDDOA11 50

VDDP11 17 Power 1.1-V (±5%) supply. Refer to or Figure 36 or Figure 37.

VDDS11 25 Power 1.1-V (±5%) supply. Refer to or Figure 36 or Figure 37.

VDDIO 16

GND Thermal

Ground.

RES0

RES2

RES3

Reserved. Tie to GND.