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1
FEATURES
TAS5086
www.ti.com
................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
PurePath Digital™ AUDIO SIX-CHANNEL PWM PROCESSOR
– Full Six-Channel Input and Output Mapping
23
• Audio Input/Output – Selectable DC Blocking Filters
– Automatic Master Clock Rate and Data • PWM Processing
Sample Rate Detection
– 8 × Oversampling With Fourth-Order Noise
– Four Serial Audio Inputs (Eight Channels) Shaping at 44.1, 48 kHz; 4 × Oversampling
at 88.2, 96 kHz; 2 × Oversampling at 176.4,
– Support for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-,
192 kHz; and 12 × Oversampling at 32 kHz
and 192-kHz Sampling Rates
– ≥ 105-dB Dynamic Range
– Data Formats: 16-, 20-, or 24-Bit Input Data;
(TAS5086+TAS5186)
Left-Justified, Right-Justified, and I
2
S
– THD < 0.06% (TAS5086 Only)
– 64- or 48-f
S
Bit-Clock Rate
– 20-Hz – 20-kHz Flat Noise Floor for 44.1-, 48-,
– 128-, 192-, 256-, 384-, and 512-f
S
Master
88.2-, 96-, 176.4- and 192-kHz Data Rates
Clock Rates (Up to a Maximum of 50 MHz)
– Digital De-Emphasis for 32-kHz, 44.1-kHz
– Six PWM Audio Output Channels
and 48-kHz Data Rates
– Any Output Channel Can be Mapped to Any
– Intelligent AM Interference Avoidance
Output Pin
System Provides Clear AM Reception
– Supports Single-Ended and Bridge-Tied
– Optimized PWM Sequence for Click- and
Loads
Popless Start and Stop
– I
2
S Serial Audio Output
– Optimized PWM Sequence for Charging of
• Audio Processing
AC-Coupling Capacitors in Single-Ended
– Volume Control Range of 48 dB to – 100 dB
Configurations
– Master Volume Control from 24 dB to – 100
– Adjustable Modulation Limit From 93.8% to
dB in 0.5-dB Increments
99.2%
– Six Individual Channel Volume Controls
• General Features
With 24-dB to – 100-dB Attenuation in
– Automated Operation With Easy-to-Use
0.5-dB Increments
Control Interface
– Serial Output Can Be Produced by
– I
2
C Serial Control Slave Interface
Downmix of 5.1-Channel Input or Fourth
– Control Interface Operational Without
Serial Input
MCLK
– 5.1-Channel Downmix to 2.1 or 3.1 PWM
– Single 3.3-V Power Supply
Output Speaker System
– 38-Pin TSSOP Package
– Integrated Bass Management
– Two Programmable Biquads in Subwoofer
Channel
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PurePath Digital is a trademark of Texas Instruments.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005 – 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

DESCRIPTION
TAS5086
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ...................................................................................................................................................
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
The TAS5086 is a six-channel digital pulse-width modulator (PWM) that provides both advanced performance
and a high level of system integration. The TAS5086 is designed to interface seamlessly with most audio digital
signal processors and MPEG decoders, accepting a wide range of input data and clock formats.
The TAS5086 drives six channels of speakers in either single-ended or bridge-tied load configurations that
accept a 1N + 1 interface format. The TAS5086 also supports 2N + 1 power stages with the use of some
external logic (e.g., TAS5112). Stereo line out in I
2
S format is available with either a pass-through signal (SDIN4)
or an internal downmix.
The TAS5086 uses AD modulation operating at a 384-kHz switching rate for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-,
and 192-kHz data. The 8 × oversampling, combined with the 4th-order noise shaper, provides a broad, flat noise
floor and excellent dynamic range from 20 Hz to 20 kHz.
The TAS5086 is only an I
2
C slave device, which always receives MCLK, SCLK, and LRCLK from other system
components. The TAS5086 accepts clock rates of 128, 192, 256, 384, and 512 f
S
. The TAS5086 accepts a 64-f
S
master clock for 176.4-kHz and 192-kHz data.
The TAS5086 accepts a 64-f
S
bit clock for all data rates. The TAS5086 also can accept a 48-f
S
SCLK rate for
MCLK ratios of 192 f
S
and 384 f
S
.
The TAS5086 is composed of five functional blocks.
• Power supply
• Clock, PLL, and serial data interface
• Serial control interface
• Device control
• PWM section
For detailed application information, see the Using the PurePath Digital PWM Processor application report
(SLEA046 ).
Figure 1 shows the functional structure of the TAS5086.
2 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5086

Chan.
1 − 6
1− 5
SDIN1
SDIN2
SDIN3
SDIN4
SDA
SCL
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
VALID1
DVDD
DVSS
DVSS_ESD
VR_DIG
VR_ANA
VR_OSC
AVDD
AVSS_PLL
SDOUT
MCLK
SCLK
LRCLK
PLLFLTP
PLLFLTM
HFCLK
OSCFLT
OSC_RES
1 LF
2 RF
3 LS
4 RS
5 C
1− 6
L’
R’
L’
R’
(L’+R’) / 2
VALID2
1 − 5
Ch
1−6
6
6
6
6
6
6
SDIN4
SDIN4
Downmix
PWM
Control
PDN
RESET
MUTE
VREG_EN
BKNDERR
Channel Six Processing
Bass Management
B0080-01
Power
Supply
Serial
Data
Interface
Channel
Selector
Block
MUX
MUX
Down−
mix
Clock Rate
/Error
Detection
and PLL
Serial
Control
Interface
System
Control
MUX
I2S Serial
Output
MUX
MUX
MUX
Vol
PWM
MUX
MUX
MUX
MUX
MUX
(L’+R’)/2
TAS5086
www.ti.com
................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
Figure 1. TAS5086 Functional Block Diagram
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TAS5086

ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TAS5086
SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ...................................................................................................................................................
www.ti.com
over operating free-air temperature range (unless otherwise noted)
(1)
DVDD and DVD_ESD – 0.3 V to 3.6 V
Supply voltage
AVDD – 0.3 V to 3.6 V
3.3-V-digital input – 0.5 V to DVDD + 0.5 V
Input voltage
5-V-tolerant
(2)
digital input – 0.5 V to 6 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> 1.8 V) ± 20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> 1.8 V) ± 20 mA
Operating free-air temperature 0 ° C to 70 ° C
Storage temperature range, T
stg
– 65 ° C to 150 ° C
(1) Stresses beyond those listed under “ absolute ratings ” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “ recommended operation conditions ”
are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are RESET, PDN, MUTE, SCLK, LRCLK, MCLK, SDA, and SCL.
T
A
≤ 25 ° C DERATING FACTOR T
A
= 70 ° C T
A
= 85 ° C
PACKAGE
POWER RATING ABOVE T
A
= 25 ° C POWER RATING POWER RATING
DBT 817.16 mW 10.214 mW/C 357.5 mW 204.29 mW
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Digital supply voltage DVDD 3 3.3 3.6 V
Analog supply voltage AVDD 3 3.3 3.6 V
V
IH
High-level input voltage 3.3-V TTL, 5-V tolerant 2 V
V
IL
Low-level input voltage 3.3-V TTL, 5-V tolerant 0.8 V
T
A
Operating ambient-air temperature range 0 25 70 ° C
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage 3.3-V TTL and 5-V
(1)
tolerant I
OH
= – 4 mA 2.4 V
V
OL
Low-level output voltage 3.3-V TTL and 5-V
(1)
tolerant I
OL
= 4 mA 0.5 V
I
OZ
High-impedance output current 3.3-V TTL 20 µ A
3.3-V TTL V
I
= V
IL
1
I
IL
Low-level input current µ A
5-V tolerant
(2)
V
I
= 0 V, DVDD = 3 V 1
3.3-V TTL V
I
= V
IH
1
I
IH
High-level input current µ A
5-V tolerant
(2)
V
I
= 5.5 V, DVDD = 3 V 20
f
S
= 48 kHz 140
f
S
= 96 kHz 150
Digital supply voltage, DVDD mA
f
S
= 192 kHz 155
I
DD
Input supply current
Power down 8
Normal 20
Analog supply voltage, AVDD mA
Power down 2
(1) 5-V-tolerant outputs are SCL and SDA
(2) 5-V-tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
4 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS5086

Serial Audio Port
t
h1
t
su1
t
su2
t
h2
SCLK
(Input)
LRCLK
(Input)
SDIN1
SDIN2
SDIN3
T0026-01
TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I
2
C-Bus
TAS5086
www.ti.com
................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008
Serial audio port slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SCLKIN
SCLK input frequency C
L
= 30 pF, SCLK = 64 f
S
2.048 12.288 MHz
t
su1
Setup time, LRCLK to SCLK rising edge 10 ns
t
h1
Hold time, LRCLK from SCLK rising edge 10 ns
t
su2
Setup time, SDIN to SCLK rising edge 10 ns
t
h2
Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 32 48 192 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%
SCLK
SCLK rising edges between LRCLK rising edges 64 64
edges
LRCLK clock edge with respect to the falling edge of SCLK
– 1/4 1/4
SCLK period
Figure 2. Slave Mode Serial Data Interface Timing
Devices
STANDARD MODE FAST MODE
PARAMETER TEST CONDITIONS UNIT
MIN MAX MIN MAX
V
IL
LOW-level input voltage – 0.5 0.3 V
DD
– 0.5 0.3 V
DD
V
V
IH
HIGH-level input voltage 0.7 V
DD
0.7 V
DD
V
V
hys
Hysteresis of Schmitt-trigger inputs N/A N/A 0.05 V
DD
V
LOW-level output voltage (open drain or
V
OL1
3-mA sink current 0 0.4 V
open collector)
Bus capacitance from 10 pF 7 + 0.1 C
b
t
of
Output fall time from V
IHmin
to
VILmax
250 250 ns
to 400 pF
(1)
t
SP
Pulse duration of spikes suppressed
(2)
N/A N/A 0 30 ns
I
i
Input current, each I/O pin – 30 30 – 30
(3)
30
(3)
µ A
C
i
Capacitance, each I/O pin 10 10 pF
(1) C
b
= capacitance of one bus line in pF. The output fall time is faster than the standard I
2
C specification.
(2) SCL and SDA have a 30-ns glitch filter.
(3) The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if V
DD
is switched off.
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TAS5086
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