TI-TAS5508C.pdf-行业报告文档类资源-CSDN文库

需积分: 5 3 浏览量 2022-12-03 19:29:00 上传评论 1 收藏 1.08MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

资源推荐

资源详情

资源评论

TAS5508C

8-Channel Digital Audio PWM Processor

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SLES257

September 2010

TAS5508C

SLES257–SEPTEMBER 2010

www.ti.com

Contents

1 Introduction PWM ............................................................................................................... 9

1.1 Features ...................................................................................................................... 9

1.2 Overview .................................................................................................................... 10

1.3 TAS5508C System Diagrams ............................................................................................ 12

2 Description ....................................................................................................................... 15

2.1 Physical Characteristics .................................................................................................. 15

2.1.1 Terminal Assignments ......................................................................................... 15

2.1.2 Ordering Information ........................................................................................... 15

2.1.3 PIN Descriptions ................................................................................................ 16

2.2 TAS5508C Functional Description ...................................................................................... 17

2.2.1 Power Supply ................................................................................................... 18

2.2.2 Clock, PLL, and Serial Data Interface ....................................................................... 18

2.2.2.1 Serial Audio Interface .............................................................................. 18

2.2.3 I

C Serial-Control Interface ................................................................................... 19

2.2.4 Device Control .................................................................................................. 19

2.2.5 Digital Audio Processor (DAP) ................................................................................ 19

2.2.5.1 TAS5508C Audio-Processing Configurations .................................................. 19

2.2.5.2 TAS5508C Audio Signal-Processing Functions ................................................ 20

2.3 TAS5508C DAP Architecture ............................................................................................ 21

2.3.1 TAS5508C DAP Architecture Diagrams ..................................................................... 21

2.3.2 I

C Coefficient Number Formats ............................................................................. 24

2.3.2.1 28-Bit 5.23 Number Format ....................................................................... 24

2.3.2.2 48-Bit 25.23 Number Format ..................................................................... 26

2.3.2.3 TAS5508C Audio Processing .................................................................... 27

2.4 Input Crossbar Mixer ...................................................................................................... 28

2.5 Biquad Filters .............................................................................................................. 28

2.6 Bass and Treble Controls ................................................................................................ 29

2.7 Volume, Automute, and Mute ............................................................................................ 30

2.8 Automute and Mute ....................................................................................................... 30

2.9 Loudness Compensation ................................................................................................. 31

2.9.1 Loudness Example ............................................................................................. 32

2.10 Dynamic Range Control (DRC) .......................................................................................... 33

2.10.1 DRC Implementation ........................................................................................... 36

2.10.2 Compression/Expansion Coefficient Computation Engine Parameters ................................. 36

2.10.2.1 Threshold Parameter Computation .............................................................. 37

2.10.2.2 Offset Parameter Computation ................................................................... 37

2.10.2.3 Slope Parameter Computation ................................................................... 38

2.11 Output Mixer ............................................................................................................... 38

2.12 PWM ........................................................................................................................ 39

2.12.1 DC Blocking (High-Pass Enable/Disable) ................................................................... 40

2.12.2 De-Emphasis Filter ............................................................................................. 40

2.12.3 Power-Supply Volume Control (PSVC) ...................................................................... 40

2.12.4 AM Interference Avoidance ................................................................................... 41

3 TAS5508C Controls and Status ........................................................................................... 43

3.1 I

C Status Registers ....................................................................................................... 43

3.1.1 General Status Register (0x01) ............................................................................... 43

TAS5508C

www.ti.com

SLES257–SEPTEMBER 2010

3.1.2 Error Status Register (0x02) .................................................................................. 43

3.2 TAS5508C Pin Controls .................................................................................................. 43

3.2.1 Reset (RESET) ................................................................................................. 43

3.2.2 Power Down (PDN) ............................................................................................ 45

3.2.3 Back-End Error (BKND_ERR) ................................................................................ 46

3.2.4 Speaker/Headphone Selector (HP_SEL) .................................................................... 46

3.2.5 Mute (MUTE) .................................................................................................... 46

3.3 Device Configuration Controls ........................................................................................... 47

3.3.1 Channel Configuration Registers ............................................................................. 47

3.3.2 Headphone Configuration Registers ......................................................................... 48

3.3.3 Audio System Configurations ................................................................................. 48

3.3.3.1 Using Line Outputs in 6-Channel Configurations .............................................. 49

3.3.4 Recovery from Clock Error .................................................................................... 49

3.3.5 Power-Supply Volume-Control Enable ....................................................................... 49

3.3.6 Volume and Mute Update Rate ............................................................................... 49

3.3.7 Modulation Index Limit ......................................................................................... 50

3.3.8 Interchannel Delay .............................................................................................. 50

3.4 Master Clock and Serial Data Rate Controls .......................................................................... 50

3.4.1 PLL Operation ................................................................................................... 51

3.5 Bank Controls .............................................................................................................. 51

3.5.1 Manual Bank Selection ........................................................................................ 52

3.5.2 Automatic Bank Selection ..................................................................................... 52

3.5.2.1 Coefficient Write Operations While Automatic Bank Switch Is Enabled .................... 52

3.5.3 Bank Set ......................................................................................................... 52

3.5.4 Bank-Switch Timeline .......................................................................................... 52

3.5.5 Bank-Switching Example 1 .................................................................................... 53

3.5.6 Bank-Switching Example 2 .................................................................................... 53

4 Electrical Specifications ..................................................................................................... 55

4.1 Absolute Maximum Ratings .............................................................................................. 55

4.2 Dissipation Rating Table (High-k Board, 105°C Junction) ........................................................... 55

4.3 Dynamic Performance At Recommended Operating Conditions at 25°C .......................................... 55

4.4 Recommended Operating Conditions .................................................................................. 55

4.5 Electrical Characteristics ................................................................................................. 56

4.6 PWM Operation ............................................................................................................ 56

4.7 Switching Characteristics ................................................................................................. 56

4.7.1 Clock Signals .................................................................................................... 56

4.7.2 Serial Audio Port ................................................................................................ 57

4.7.3 I

C Serial Control Port Operation ............................................................................. 58

4.7.4 Reset Timing (RESET) ......................................................................................... 59

4.7.5 Power-Down (PDN) Timing ................................................................................... 59

4.7.6 Back-End Error (BKND_ERR) ................................................................................ 60

4.7.7 Mute Timing (MUTE) ........................................................................................... 60

4.7.8 Headphone Select (HP_SEL) ................................................................................. 61

4.7.9 Volume Control ................................................................................................. 62

4.8 Serial Audio Interface Control and Timing ............................................................................. 62

4.8.1 I

S Timing ....................................................................................................... 62

4.8.2 Left-Justified Timing ............................................................................................ 63

TAS5508C

SLES257–SEPTEMBER 2010

www.ti.com

4.8.3 Right-Justified Timing .......................................................................................... 64

5 I

C Serial-Control Interface (Slave Address 0x36) .................................................................. 65

5.1 General I

C Operation .................................................................................................... 65

5.2 Single- and Multiple-Byte Transfers ..................................................................................... 65

5.3 Single-Byte Write .......................................................................................................... 66

5.4 Multiple-Byte Write ........................................................................................................ 66

5.5 Incremental Multiple-Byte Write ......................................................................................... 67

5.6 Single-Byte Read .......................................................................................................... 67

5.7 Multiple-Byte Read ........................................................................................................ 68

6 Serial-Control I

C Register Summary ................................................................................... 69

7 Serial-Control Interface Register Definitions ......................................................................... 73

7.1 Clock Control Register (0x00) ........................................................................................... 73

7.2 General Status Register 0 (0x01) ....................................................................................... 73

7.3 Error Status Register (0x02) ............................................................................................. 74

7.4 System Control Register 1 (0x03) ....................................................................................... 74

7.5 System Control Register 2 (0x04) ....................................................................................... 74

7.6 Channel Configuration Control Registers (0x05–0x0C) .............................................................. 74

7.7 Headphone Configuration Control Register (0x0D) ................................................................... 75

7.8 Serial Data Interface Control Register (0x0E) ......................................................................... 75

7.9 Soft Mute Register (0x0F) ................................................................................................ 76

7.10 Automute Control Register (0x14) ....................................................................................... 77

7.11 Automute PWM Threshold and Back-End Reset Period Register (0x15) .......................................... 78

7.12 Modulation Index Limit Register (0x16) ................................................................................. 79

7.13 Interchannel Delay Registers (0x1B–0x22) ............................................................................ 79

7.14 Channel Offset Register (0x23) .......................................................................................... 79

7.15 Bank-Switching Command Register (0x40) ............................................................................ 80

7.16 Input Mixer Registers, Channels 1–8 (0x41–0x48) ................................................................... 80

7.17 Bass Management Registers (0x49–0x50) ............................................................................ 84

7.18 Biquad Filter Register (0x51–0x88) ..................................................................................... 84

7.19 Bass and Treble Bypass Register, Channels 1–8 (0x89–0x90) ..................................................... 85

7.20 Loudness Registers (0x91–0x95) ....................................................................................... 85

7.21 DRC1 Control Registers, Channels 1–7 (0x96) ....................................................................... 86

7.22 DRC2 Control Register, Channel 8 (0x97) ............................................................................. 87

7.23 DRC1 Data Registers (0x98–0x9C) ..................................................................................... 87

7.24 DRC2 Data Registers (0x9D–0xA1) .................................................................................... 88

7.25 DRC Bypass Registers (0xA2–0xA9) ................................................................................... 88

7.26 8×2 Output Mixer Registers (0xAA–0xAF) ............................................................................. 88

7.27 8×3 Output Mixer Registers (0xB0–0xB1) ............................................................................. 89

7.28 Volume Biquad Register (0xCF) ......................................................................................... 91

7.29 Volume, Treble, and Bass Slew Rates Register (0xD0) ............................................................. 92

7.30 Volume Registers (0xD1–0xD9) ......................................................................................... 92

7.31 Bass Filter Set Register (0xDA) ......................................................................................... 94

7.32 Bass Filter Index Register (0xDB) ....................................................................................... 95

7.33 Treble Filter Set Register (0xDC) ....................................................................................... 96

7.34 Treble Filter Index (0xDD) ................................................................................................ 97

7.35 AM Mode Register (0xDE) ............................................................................................... 97

剩余107页未读，继续阅读

评论收藏

内容反馈

不觉明了

粉丝: 626
资源: 3706

会员权益专享

TI-TAS5508C.pdf

mate40pro 高维禁用_NOH-AN00 102.0.0.168_Firmware_05016QEW

罗克韦尔自动化-智能化罐区自动化(i-TAS)系统解决方案.pdf

Cla--tas-2020年拉美裔营销报告（英文）-2020.12-22页精品报告2020.pdf

XX公司大数据平台需求规格说明书-TAS.zip程序开发文档软件开发文技术档下载

cs310-TAS-Project-sp21-源码.rar

TAS1020B-Firmware-Development-Kit.zip_TI_audio usb_tas1020b fi

基于任务驱动的机载相控阵雷达TAS调度算法.pdf

tas5825m.pdf

使用InduAsisit进行Hella TAS-71版本标定流程.pdf

易语言\Super-EC5.0正版.

罗克韦尔智能化罐区自动化(i-TAS)系统解决方案.zip

Transmit-antenna-selection-systems.zip_Single and Single_TAS_TAS

TI-TAS5828M中文版

产品数据管理与企业资源计划系统间更改信息的集成与控制

基于Web的企业资源计划(ERP)系统设计与实现

从高层支持到企业资源计划系统(ERP)吸收-基于系统优势和组织吸收能力的中介分析

由于找不到iUtils.dll,无法继续执行代码

python大作业 含爬虫、数据可视化、地图、报告、及源码（2016-2021全国各地区粮食产量）.rar

SnapGene6.0.2 软件安装包 文本附带下载链接 有蓝奏云和百度云两种下载方式

雷暴熊与门_v3.0.3.0-clbox.exe

2020最新华为IPD流程管理(完整修定版)PDF

AEyeNoPluginSetup(人脸驱动).exe

Academic+Phrasebank+2021 写作指导材料 2021英原版+2021中英文对照翻译版

会员权益专享

最新资源

python大作业含爬虫、数据可视化、地图、报告、及源码（2016-2021全国各地区粮食产量）.rar

SnapGene6.0.2 软件安装包文本附带下载链接有蓝奏云和百度云两种下载方式