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Copyright © 2016, Texas Instruments Incorporated
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PGA2311
SBOS218D –DECEMBER 2001–REVISED MAY 2016
PGA2311
Stereo Audio Volume Control
1
1 Features
1
• Digitally-Controlled Analog Volume Control:
– Two Independent Audio Channels
– Serial Control Interface
– Zero Crossing Detection
– Mute Function
• Wide Gain and Attenuation Range:
+31.5 dB to −95.5 dB with 0.5-dB Steps
• Low Noise and Distortion:
– 120-dB Dynamic Range
– 0.0004% THD+N at 1 kHz (U-Grade)
– 0.0002% THD+N at 1 kHz (A-Grade)
• Noise-Free Level Transitions
• Low Interchannel Crosstalk: −130 dBFS
• Power Supplies: ±5-V Analog, +5-V Digital
• Available in PDIP-16 and SOIC-16 Packages
• Pin- and Software-Compatible With the Crystal
CS3310
2 Applications
• Audio Amplifiers
• Mixing Consoles
• Multi-Track Recorders
• Broadcast Studio Equipment
• Musical Instruments
• Effects Processors
• A/V Receivers
• Car Audio Systems
3 Description
The PGA2311 device is a high-performance, stereo
audio volume control designed for professional and
high-end consumer audio systems. The PGA2311
uses an internal high-performance operational
amplifier to yield low noise and distortion. The
PGA2311 also provides the capability to drive 660-Ω
loads directly without buffering. The 3-wire serial
control interface allows for connection to a wide
variety of host controllers, in addition to support for
daisy-chaining of multiple PGA2311 devices.
Device Information
(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
PGA2311
SOIC (16) 7.5 mm × 10.30 mm
PDIP (16) 6.35 mm × 19.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Stereo Audio Volume Control

2
PGA2311
SBOS218D –DECEMBER 2001–REVISED MAY 2016
www.ti.com
Product Folder Links: PGA2311
Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 8
7 Detailed Description............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
7.5 Programming .......................................................... 12
8 Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 15
11 Device and Documentation Support ................. 16
11.1 Documentation Support ....................................... 16
11.2 Community Resources.......................................... 16
11.3 Trademarks........................................................... 16
11.4 Electrostatic Discharge Caution............................ 16
11.5 Glossary................................................................ 16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2016) to Revision D Page
• Changed the values of Voltage range, PGA2311PA, UA (A−grade) To: (V
A
-) = + 1.25 V, and (V
A
-) = –1.25 V in the
Electrical Characteristics table ............................................................................................................................................... 5
• Chnaged the Quiescent current Test Conditions To: V
A
= +5 V, and V
A
= –5 V in the Electrical Characteristics table ....... 6
Changes from Revision B (January 2016) to Revision C Page
• Changed package family terms in second to last Features bullet ......................................................................................... 1
• Changed description of pin 7 in Pin Functions table ............................................................................................................. 3
• Deleted lead temperature and package temperature rows from Absolute Maximum Ratings table...................................... 4
Changes from Revision A (June 2002) to Revision B Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1

3
PGA2311
www.ti.com
SBOS218D –DECEMBER 2001–REVISED MAY 2016
Product Folder Links: PGA2311
Submit Documentation FeedbackCopyright © 2001–2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
N or DW Package
16-Pin PDIP or SOIC
Top View
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 ZCEN I Zero-crossing enable input (active high)
2 CS I Chip-select input (active low)
3 SDI I Serial data input
4 V
D
+ I Digital power supply, +5 V
5 DGND — Digital ground
6 SCLK I Serial clock input
7 SDO O Serial data output
8 MUTE I Mute control input (active low)
9 V
IN
R I Analog input, right channel
10 AGNDR — Analog ground, right channel
11 V
OUT
R O Analog output, right channel
12 V
A
+ I Analog power supply, +5 V
13 V
A
– I Analog power supply, –5 V
14 V
OUT
L O Analog output, left channel
15 AGNDL — Analog ground, left channel
16 V
IN
L I Analog input, left channel

4
PGA2311
SBOS218D –DECEMBER 2001 –REVISED MAY 2016
www.ti.com
Product Folder Links: PGA2311
Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN MAX UNIT
Supply voltage
V
A
+ 5.5
V
V
A
– –5.5
V
D
+ 5.5
V
A
+ to V
D
+ < ± 0.3
Analog input voltage 0 V
A
+, V
A
− V
Digital input voltage –0.3 V
D
+ V
Operating temperature –40 85 °C
Junction temperature 150 °C
Storage temperature, T
stg
–65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE UNIT
PGA2311 in 16-Pin SOIC Package
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
±1500
PGA2311 in 16-Pin PDIP Package
V
(ESD)
Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000 V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
A
+ Positive analog power supply 4.75 5 5.25 V
V
A
– Negative analog power supply –4.75 –5 –5.25 V
V
D
+ Digital power supply 4.75 5 5.25 V
Operating temperature –40 25 85 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC
(1)
PGA2311
UNITN (PDIP) DW (SOIC)
16 PINS 16 PINS
R
θJA
Junction-to-ambient thermal resistance 39.9 83 °C/W
R
θJC(top)
Junction-to-case (top) thermal resistance 26.2 44 °C/W
R
θJB
Junction-to-board thermal resistance 20.1 40.5 °C/W
ψ
JT
Junction-to-top characterization parameter 10.7 11.5 °C/W
ψ
JB
Junction-to-board characterization parameter 19.9 40.2 °C/W
R
θJC(bot)
Junction-to-case (bottom) thermal resistance — — °C/W

5
PGA2311
www.ti.com
SBOS218D –DECEMBER 2001–REVISED MAY 2016
Product Folder Links: PGA2311
Submit Documentation FeedbackCopyright © 2001–2016, Texas Instruments Incorporated
6.5 Electrical Characteristics
At T
A
= +25°C, V
A
+ = +5 V, V
A
− = –5 V, V
D
+ = +5 V, R
L
= 100 kΩ, C
L
= 20 pF, BW measure = 10 Hz to 20 kHz, unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC CHARACTERISTICS
Step size 0.5 dB
Gain error Gain setting = 31.5 dB ±0.05 dB
Gain matching ±0.05 dB
Input resistance 10 kΩ
Input capacitance
PGA2311P, U (U−grade) 3
pF
PGA2311PA, UA (A−grade) 7
AC CHARACTERISTICS
THD+N
V
IN
= 2 Vrms,
f = 1 kHz
PGA2311P,
U (U−grade)
0.0004% 0.001%
PGA2311PA,
UA (A−grade)
0.0002% 0.0004%
Dynamic range V
IN
= AGND, gain = 0 dB 116 120 dB
Voltage range, output
PGA2311P, U (U−grade) (V
A
−) + 1.25 (V
A
+) –1.25
V
PGA2311PA, UA (A−grade) (V
A
−) + 1.25 (V
A
−) − 1.25
Voltage range, input
(without clipping)
2.5 Vrms
Output noise V
IN
= AGND, gain = 0 dB 2.5 4 μV
RMS
Interchannel crosstalk f = 1 kHz –130 dBFS
OUTPUT BUFFER
Offset voltage V
IN
= AGND, gain = 0 dB 0.25 0.5 mV
Load capacitance stability 100 pF
Short-circuit current 50 mA
Unity-gain bandwidth, small signal 10 MHz
DIGITAL CHARACTERISTICS
V
IH
High-level input voltage 2 V
D
+ V
V
IL
Low-level input voltage –0.3 0.8 V
V
OH
High-level output voltage I
O
= 200 μA
PGA2311P,
U (U−grade)
(V
A
+) − 1
V
PGA2311PA,
UA (A−grade)
(V
D
+) − 1
V
OL
Low-level output voltage I
O
= –3.2 mA 0.4 V
Input leakage current 1 10 µA
SWITCHING CHARACTERISTICS
f
SCLK
Serial clock (SCLK) frequency 0 6.25 MHz
t
PL
SCLK pulse duration low 80 ns
t
PH
SCLK pulse duration high 80 ns
t
MI
MUTE pulse duration low 2 ms
INPUT TIMING
t
SDS
SDI setup time 20 ns
t
SDH
SDI hold time 20 ns
t
CSCR
CS falling to SCLK rising 90 ns
t
CFCS
SCLK falling to CS rising 35 ns
OUTPUT TIMING
t
CSO
CS low to SDO active 35 ns
t
CFDO
SCLK falling to SDO data valid 60 ns
t
CSZ
CS high to SDO high impedance 100 ns
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