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FEATURES
D DIGITALLY-CONTROLLED ANALOG VOLUME
CONTROL:
Two Independent Audio Channels
Serial Control Interface
Zero Crossing Detection
Mute Function
D WIDE GAIN AND ATTENUATION RANGE:
+31.5dB to −95.5dB with 0.5dB Steps
D LOW NOISE AND DISTORTION:
120dB Dynamic Range
0.0003% THD+N at 1kHz
D LOW INTERCHANNEL CROSSTALK:
−126dBFS
D NOISE-FREE LEVEL TRANSITIONS
D POWER SUPPLIES: +15V Analog, +5V Digital
D AVAILABLE IN SOL−16 PACKAGE
D PIN-FOR-PIN COMPATIBLE WITH THE
PGA2310
APPLICATIONS
D AUDIO AMPLIFIERS
D MIXING CONSOLES
D MULTI-TRACK RECORDERS
D BROADCAST STUDIO EQUIPMENT
D MUSICAL INSTRUMENTS
D EFFECTS PROCESSORS
D A/V RECEIVERS
D CAR AUDIO SYSTEMS
DESCRIPTION
The PGA2320 is a high-performance, stereo audio volume
control designed for professional and high-end consumer
audio systems. The ability to operate from ±15V analog
power supplies enables the PGA2320 to process input
signals with large voltage swings, thereby preserving the
dynamic range available in the overall signal path. Using
high performance operational amplifier stages internal to
the PGA2320 yields low noise and distortion, while
providing the capability to drive 600Ω loads directly
without buffering. The three-wire serial control interface
allows for connection to a wide variety of host controllers,
in addition to support for daisy-chaining of multiple
PGA2320 devices.
PGA2320
SBOS312B − JULY 2004 − REVISED DECEMBER 2004
Stereo Audio Volume Control
www.ti.com
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
! !

"#$#%
SBOS312B − JULY 2004 − REVISED DECEMBER 2004
www.ti.com
2
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
PGA2320 UNIT
V
A
+ +15.5 V
Supply voltage
V
A
− −15.5 V
Supply voltage
V
D
+ +5.5 V
Analog input voltage 0 to V
A
+, V
A
− V
Digital input voltage −0.3 to V
D
+ V
Operating temperature range −40 to +85 °C
Storage temperature range −65 to +150 °C
Junction temperature +150 °C
Lead temperature (soldering, 10s) +300 °C
Package temperature (IR, reflow, 10s) +235 °C
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this data
sheet.

"#$#%
SBOS312B − JULY 2004 − REVISED DECEMBER 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS
At T
A
= +25°C, V
A
+ = +15V, V
A
− = −15V, V
D
+ = +5V, R
L
= 100kΩ, C
L
= 20pF, BW measure = 20Hz to 20kHz, unless otherwise noted.
PGA2320
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC CHARACTERISTICS
Step Size 0.5 dB
Gain Error Gain Setting = 31.5dB ±0.1 dB
Gain Matching ±0.1 dB
Input Resistance 12 kΩ
Input Capacitance 18 pF
AC CHARACTERISTICS
THD+N V
IN
= 10V
PP
, f = 1kHz 0.0003 0.001 %
Dynamic Range V
IN
= AGND, Gain = 0dB 115 120 dB
Voltage Range, Input and Output (V
A
−) + 0.86 (V
A
+) − 0.86 V
Output Noise V
IN
= AGND, Gain = 0dB 10.5 17.5 µV
RMS
Interchannel Crosstalk f = 1kHz −126 dBFS
OUTPUT BUFFER
Offset Voltage V
IN
= AGND, Gain = 0dB 1 7.5 mV
Load Capacitance Stability 1000 pF
Short-Circuit Current 75 mA
Unity-Gain Bandwidth, Small Signal 1 MHz
DIGITAL CHARACTERISTICS
High-Level Input Voltage, V
IH
+2.0 V
D
+ V
Low-Level Input Voltage, V
IL
−0.3 0.8 V
High-Level Output Voltage, V
OH
I
O
= 200µA (V
D
+) − 1.0 V
Low-Level Output Voltage, V
OL
I
O
= −2mA 0.4 V
Input Leakage Current 1 10 µA
SWITCHING CHARACTERISTICS
Serial Clock (SCLK) Frequency t
SCLK
0 6.25 MHz
Serial Clock (SCLK) Pulse Width Low t
PH
80 ns
Serial Clock (SCLK) Pulse Width
High
t
PL
80 ns
MUTE Pulse Width Low t
MI
2.0 ms
Input Timing
SDI Setup Time t
SDS
20 ns
SDI Hold Time t
SDH
20 ns
CS Falling to SCLK Rising t
CSCR
90 ns
SCLK Falling to CS Rising t
CFCS
35 ns
Output Timing
CS Low to SDO Active t
CSO
35 ns
SCLK Falling to SDO Data Valid t
CFDO
60 ns
POWER SUPPLY
Operating Voltage
V
A
+ +4.5 +15 +15.5 V
V
A
− −4.5 −15 −15.5 V
V
D
+ +4.5 +5 +5.5 V
Quiescent Current
I
A
+ V
A
+ = +15V 11 16 mA
I
A
− V
A
− = −15V 11 16 mA
I
D
+ V
D
+ = +5V 0.6 1.5 mA

"#$#%
SBOS312B − JULY 2004 − REVISED DECEMBER 2004
www.ti.com
4
PIN CONFIGURATION
Top View
ZCEN
CS
SDI
V
D
+
DGND
SCLK
SDO
MUTE
V
IN
L
AGNDL
V
OUT
L
V
A
−
V
A
+
V
OUT
R
AGNDR
V
IN
R
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGA2320
PIN ASSIGNMENTS
PIN NAME FUNCTION
1 ZCEN Zero Crossing Enable Input (Active High)
2 CS Chip-Select Input (Active Low)
3 SDI Serial Data input
4 V
D
+ Digital Power Supply, +5V
5 DGND Digital Ground
6 SCLK Serial Clock Input
7 SDO Serial Data Output
8 MUTE Mute Control Input (Active Low)
9 V
IN
R Analog Input, Right Channel
10 AGNDR Analog Ground, Right Channel
11 V
OUT
R Analog Output, Right Channel
12 V
A
+ Analog Power Supply, +15V
13 V
A
− Analog Power Supply, −15V
14 V
OUT
L Analog Output, Left Channel
15 AGNDL Analog Ground, Left Channel
16 V
IN
L Analog Input, Left Channel

"#$#%
SBOS312B − JULY 2004 − REVISED DECEMBER 2004
www.ti.com
5
TYPICAL CHARACTERISTICS
At T
A
= +25°C, V
A
+ = +15V, V
A
− = −15V, V
D
+ = +5V, R
L
= 100kΩ, C
L
= 20pF, BW measure = 20Hz to 20kHz, unless otherwise noted.
FREQUENCY RESPONSE (0dB = 6.0V
RMS
)
GAIN = 0dB
Frequency (Hz)
Amplitude (dB)
1.0
0.8
0.6
0.4
0.2
0
−
0.2
−
0.4
−
0.6
−
0.8
−
1.0
1k 10k10010 100k 200k
THD+N vs INPUT AMPLITUDE
(Gain = 0dB, f = 1kHz)
Input Amplitude (V
RMS
)
THD+N (%)
0.1
0.01
0.001
0.0001
1100m 10
THD+N vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 3.0V
RMS
,R
L
=100k
Ω
)
Input Frequency (Hz)
THD+N (%)
0.01
0.001
0.0001
1k10020 10k 20k
THD+N vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 3.0V
RMS
,R
L
=600
Ω
)
Input Frequency (Hz)
THD+N (%)
0.01
0.001
0.0001
1k10020 10k 20k
THD+N vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 8.5V
RMS
,R
L
=100k
Ω
)
Input Frequency (Hz)
THD+N (%)
0.01
0.001
0.0001
1k10020 10k 20k
THD+N vs INPUT FREQUENCY
(Gain = 0dB, Amplitude = 8.5V
RMS
,R
L
=600
Ω
)
Input Frequency (Hz)
THD+N (%)
0.01
0.001
0.0001
1k10020 10k 20k
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