1 8
2 7
3 6
4 5
CDCS503-Q1
IN
SSC_SEL 0
SSC_SEL 1
GND
VDD
OE
OUT
FS
CDCS503-Q1
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ZHCS946B –MARCH 2012–REVISED JUNE 2012
这些装置包含有限的内置 ESD 保护。
存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损伤。
DEVICE INFORMATION
PACKAGE
PIN FUNCTIONS
SIGNAL PIN TYPE DESCRIPTION
IN 1 I LVCMOS clock input
OUT 6 O LVCMOS clock output
SSC_SEL 0, 1 2, 3 I Spread selection pins, internal pullup
OE 7 I Output enable, internal pullup
FS 5 I Frequency multiplication selection, internal pullup
VDD 8 Power 3.3-V power supply
GND 4 Ground Ground
ORDERING INFORMATION
T
A
PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 105°C TSSOP 2000 CDCS503TPWRQ1 CS503Q
PACKAGE THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE
over operating free-air temperature range (unless otherwise noted)
(1)
THERMAL AIRFLOW (CFM)
PW 8-PIN TSSOP UNIT
0 150 250 500
High K 149 142 138 132
R
θJA
°C/W
Low K 230 185 170 150
High K 65
R
θJC
°C/W
Low K 69
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
THERMAL INFORMATION
CDCS503TPWRQ1
THERMAL METRIC
(1)
UNIT
PW (8 PINS)
θ
JA
Junction-to-ambient thermal resistance 179.9
θ
JCtop
Junction-to-case (top) thermal resistance 64.9
θ
JB
Junction-to-board thermal resistance 108.7
°C/W
ψ
JT
Junction-to-top characterization parameter 9
ψ
JB
Junction-to-board characterization parameter 107
θ
JCbot
Junction-to-case (bottom) thermal resistance n/a
(1) 有关传统和全新热度量的更多信息,请参阅 IC
封装热度量
应用报告 (文献号:SPRA953)。
Copyright © 2012, Texas Instruments Incorporated 3
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