DDR控制器MIG IP破解（完整破解verilog）

in_fifo_001.vp.v in_fifo_002.wp.v iserdese2_001.vp.v iserdese2_002.vp.v oserdese2_001.vp.v oserdese2_002.vp.v out_fifo_ 001.vp.v out_fifo_002.vp.v phaser_in_001.vp.v phaser_in_002.vp.v phaser_out 001.vp.v phaser _out 002.vp.v phy_control_001.vp.v phy_control_002.vp.v PHY (version 1).xlsx（目录表格）