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xilinx fpga gt wizard serdes手册 用于Xilinx开发查看
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7 Series FPGAs Transceivers
Wizard v3.6
LogiCORE IP Product Guide
Vivado Design Suite
PG168 November 30, 2016
7 Series FPGAs Transceivers Wizard v3.6 www.xilinx.com 2
PG168 November 30, 2016
Table of Contents
IP Facts
Chapter 1: Overview
About the Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 2: Product Specification
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset Sequence Modules for GTH and GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Chapter 5: Example Design
Functional Simulation Using the Vivado Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Implementing Using the Vivado Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Timing Simulation Using the Vivado Design Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Using Vivado Design Suite Debug Feature with the Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Directory and File Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Output Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Directory and File Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Example Design Description for GTX, GTH, and GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Send Feedback
7 Series FPGAs Transceivers Wizard v3.6 www.xilinx.com 3
PG168 November 30, 2016
Reset Sequence Modules for GTH and GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Example Design Description for GTZ Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Known Limitations of the GTZ Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Known Limitations of the Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Appendix A: Verification, Compliance, and Interoperability
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Hardware Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Appendix B: Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Wizard Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Next Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Loopback Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
GT Debug Using IBERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Debugging Using Serial I/O Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Debugging Using Embedded BERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7 Series GT Wizard Hardware Validation on the KC705 Evaluation Board . . . . . . . . . . . . . . . . . . 127
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Send Feedback
7 Series FPGAs Transceivers Wizard v3.6 www.xilinx.com 4
PG168 November 30, 2016 Product Specification
Introduction
The 7 series FPGAs Transceivers Wizard
LogiCORE™ IP automates the task of creating
HDL wrappers to configure Xilinx® 7 series
FPGA on-chip transceivers. The wizard
customization Vivado® Integrated Design
Environment (IDE) allows you to configure one
or more high-speed serial transceivers using
either pre-defined templates supporting
popular industry standards, or from scratch to
support a wide variety of custom protocols.
IMPORTANT: Download the most up-to-date IP
update before using the Wizard.
Features
• Creates customized HDL wrappers to
configure high-speed serial transceivers in
7 series FPGAs.
• Automatically configures analog settings.
• Predefined templates are provided for
Aurora 8B/10B, Aurora 64B/66B, CEI-6G,
DisplayPort, Interlaken, Open Base Station
Architecture Initiative (OBSAI), OC192,
OC48, SRIO, 10GBASE-R, Common Packet
Radio Interface (CPRI), Gigabit Ethernet,
10 Gb Attachment Unit Interface (XAUI),
RXAUI, and XLAUI, OTU3, 10GH Small
Form-factor Pluggable Plus (SFP+), Optical
Transport Network OTU3, V-by-One, SDI,
and others as well as custom protocol using
start from scratch.
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
Artix®-7, Kintex®-7, and Virtex®-7 FPGAs, and
Zynq All Programmable SoCs
Supported User
Interfaces
Not Applicable
Resources
Provided with Core
Design Files RTL
Example Design
Verilog and VHDL
(Only Verilog is supported for GTZ transceivers)
Test Bench
Verilog and VHDL
(Only Verilog is supported for GTZ transceivers)
Constraints File XDC
Simulation
Model
None
Supported
S/W Driver
(2)
Not Applicable
Tested Design Flows
(2)
Design Entry Vivado Design Suite
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide
.
Synthesis Vivado Synthesis.
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide
.
Send Feedback
7 Series FPGAs Transceivers Wizard v3.6 www.xilinx.com 5
PG168 November 30, 2016
Chapter 1
Overview
The 7 series FPGAs Transceivers Wizard (Wizard) can be used to configure one or more
Virtex®-7, Kintex®-7, Artix®-7, and Zynq®-7000 device transceivers. Start from scratch, or
use an industry-standard template to configure 7 series FPGA transceiver cores. The Wizard
generates a custom wrapper for the transceivers with all inputs given through the
transceiver wizard Vivado® IDE. In addition, the wizard generates an example design, test
bench, and scripts to observe the transceivers operating under simulation and in hardware.
About the Wizard
The 7 series FPGAs Transceiver Wizard automates the task of creating HDL wrappers to
configure the high-speed serial transceivers in Artix-7, Kintex-7, and Virtex-7 FPGAs.
The menu-driven interface allows you to configure one or more transceivers using
predefined templates for popular industry standards, or by using custom templates, to
support a wide variety of custom protocols. The Wizard produces a wrapper, an example
design, and a test bench for rapid integration and verification of the serial interface with
your custom function.
The Wizard produces a wrapper that instantiates one or more properly configured
transceivers for custom applications (Figure 1-1).
Send Feedback
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- 甜甜不加糖2023-07-26不仅提供了详细的步骤和操作说明,而且还解答了常见的疑问,非常贴心。
- 月小烟2023-07-26文件中的图表和插图清晰明了,使得阅读更加直观易懂。
- 啊看看2023-07-26文件中的示例和案例分析非常实用,让人更好地理解和运用GT Wizard。
- 蓝洱2023-07-26这个文件提供了许多有用的信息,对于理解和应用GT Wizard技术非常有帮助。
- 老许的花开2023-07-26我发现这个文件的编排非常合理,可以很容易地找到所需的信息。
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