基于FPGA的电子时钟（6位数码管）.zip
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2021-06-25
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基于FPGA的电子时钟（6位数码管）.zip （578个子文件） 
__synthesis_is_complete__ 0B _info 14KB _info 13KB _info 8KB _info 7KB _info 7KB _info 6KB _info 5KB _info 5KB _info 5KB _info 4KB _info 3KB _info 1KB _sdfmsgdata 32B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B _vmake 29B digital_clock.root_partition.cmp.ammdb 2KB digital_clock.vpr.ammdb 2KB digital_clock.map.ammdb 129B int_div.v.bak 2KB int_div_show.v.bak 2KB music1.v.bak 2KB music2.v.bak 2KB music.v.bak 2KB digital_clock_run_msim_rtl_verilog.do.bak 2KB modify.v.bak 2KB digital_hour_minute_second_TB.v.bak 1KB clock_beer.v.bak 1KB digital_test_TB.v.bak 1KB clock_plus.v.bak 1004B modify_clock_cls.v.bak 969B bell.v.bak 961B clock_test.v.bak 807B clock.v.bak 807B digital_clock_run_msim_gate_verilog.do.bak 694B send_data.v.bak 663B digital_bit_6.v.bak 541B decode_segment.v.bak 539B digital_bit.v.bak 533B control_music.v.bak 435B modify_clock.v.bak 416B led.v.bak 316B choose_music.v.bak 308B int_div_TB.v.bak 287B int_div_show_TB.v.bak 280B select_bit.v.bak 243B digital_TB.v.bak 242B beer.v.bak 228B music_TB.v.bak 226B FFT_T.v.bak 204B change_state.v.bak 179B digital_clock_run_msim_rtl_verilog.do.bak1 2KB digital_clock_run_msim_gate_verilog.do.bak1 694B digital_clock_run_msim_rtl_verilog.do.bak10 3KB digital_clock_run_msim_gate_verilog.do.bak10 694B digital_clock_run_msim_rtl_verilog.do.bak11 3KB digital_clock_run_msim_gate_verilog.do.bak11 694B digital_clock_run_msim_rtl_verilog.do.bak2 2KB digital_clock_run_msim_gate_verilog.do.bak2 694B digital_clock_run_msim_rtl_verilog.do.bak3 2KB digital_clock_run_msim_gate_verilog.do.bak3 694B digital_clock_run_msim_rtl_verilog.do.bak4 2KB digital_clock_run_msim_gate_verilog.do.bak4 694B digital_clock_run_msim_rtl_verilog.do.bak5 2KB digital_clock_run_msim_gate_verilog.do.bak5 694B digital_clock_run_msim_rtl_verilog.do.bak6 2KB digital_clock_run_msim_gate_verilog.do.bak6 694B digital_clock_run_msim_rtl_verilog.do.bak7 2KB digital_clock_run_msim_gate_verilog.do.bak7 694B digital_clock_run_msim_rtl_verilog.do.bak8 2KB digital_clock_run_msim_gate_verilog.do.bak8 694B digital_clock_run_msim_rtl_verilog.do.bak9 2KB digital_clock_run_msim_gate_verilog.do.bak9 694B runme.bat 229B digital_clock.bdf 32KB digital_clock_6.bdf 16KB digital_clock.cmp.bpm 1KB digital_clock.map.bpm 964B modify_clock_cls.bsf 3KB clock.bsf 3KB clock_test.bsf 3KB send_data.bsf 3KB send_data_6.bsf 3KB music2.bsf 3KB modify_clock.bsf 3KB music1.bsf 2KB music.bsf 2KB modify.bsf 2KB clock_plus.bsf 2KB clock_beer.bsf 2KB共 578 条
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