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PCI Local Bus Specification

Revision 3.0

February 3, 2004

PCI LOCAL BUS SPECIFICATION, REV. 3.0

Contents

PREFACE ........................................................................................................................ 13

PECIFICATION

............................................................................................................... 13

NCORPORATION OF

NGINEERING

HANGE

OTICES

(ECN

)....................................... 13

OCUMENT

ONVENTIONS

............................................................................................ 14

1. INTRODUCTION................................................................................................... 15

1.1. S

PECIFICATION

ONTENTS

................................................................................. 15

1.2. M

OTIVATION

...................................................................................................... 15

1.3. PCI L

OCAL

PPLICATIONS

......................................................................... 16

1.4. PCI L

OCAL

VERVIEW

............................................................................... 17

1.5. PCI L

OCAL

EATURES AND

ENEFITS

........................................................ 18

1.6. A

DMINISTRATION

............................................................................................... 20

2. SIGNAL DEFINITION .......................................................................................... 21

2.1. S

IGNAL

YPE

EFINITION

.................................................................................. 22

2.2. P

UNCTIONAL

ROUPS

.................................................................................. 22

2.2.1. System Pins................................................................................................ 23

2.2.2. Address and Data Pins.............................................................................. 24

2.2.3. Interface Control Pins............................................................................... 25

2.2.4. Arbitration Pins (Bus Masters Only) ........................................................ 27

2.2.5. Error Reporting Pins................................................................................. 27

2.2.6. Interrupt Pins (Optional) .......................................................................... 28

2.2.7. Additional Signals ..................................................................................... 31

2.2.8. 64-Bit Bus Extension Pins (Optional) ....................................................... 33

2.2.9. JTAG/Boundary Scan Pins (Optional)...................................................... 34

2.2.10. System Management Bus Interface Pins (Optional) ................................. 35

2.3. S

IDEBAND

IGNALS

............................................................................................ 36

2.4. C

ENTRAL

ESOURCE

UNCTIONS

....................................................................... 36

3. BUS OPERATION.................................................................................................. 37

3.1. B

OMMANDS

................................................................................................ 37

3.1.1. Command Definition ................................................................................. 37

3.1.2. Command Usage Rules ............................................................................. 39

3.2. PCI P

ROTOCOL

UNDAMENTALS

....................................................................... 42

3.2.1. Basic Transfer Control.............................................................................. 43

3.2.2. Addressing................................................................................................. 44

3.2.3. Byte Lane and Byte Enable Usage ............................................................ 56

3.2.4. Bus Driving and Turnaround .................................................................... 57

3.2.5. Transaction Ordering and Posting ........................................................... 58

3.2.6. Combining, Merging, and Collapsing....................................................... 62

PCI LOCAL BUS SPECIFICATION, REV. 3.0

3.3. B

RANSACTIONS

........................................................................................... 64

3.3.1. Read Transaction ...................................................................................... 65

3.3.2. Write Transaction...................................................................................... 66

3.3.3. Transaction Termination........................................................................... 67

3.4. A

RBITRATION

..................................................................................................... 87

3.4.1. Arbitration Signaling Protocol.................................................................. 89

3.4.2. Fast Back-to-Back Transactions ............................................................... 91

3.4.3. Arbitration Parking................................................................................... 94

3.5. L

ATENCY

............................................................................................................ 95

3.5.1. Target Latency........................................................................................... 95

3.5.2. Master Data Latency................................................................................. 98

3.5.3. Memory Write Maximum Completion Time Limit.....................................99

3.5.4. Arbitration Latency ................................................................................. 100

3.6. O

THER

PERATIONS

................................................................................. 110

3.6.1. Device Selection ...................................................................................... 110

3.6.2. Special Cycle ........................................................................................... 111

3.6.3. IDSEL Stepping....................................................................................... 113

3.6.4. Interrupt Acknowledge ............................................................................ 114

3.7. E

RROR

UNCTIONS

........................................................................................... 115

3.7.1. Parity Generation.................................................................................... 115

3.7.2. Parity Checking....................................................................................... 116

3.7.3. Address Parity Errors ............................................................................. 116

3.7.4. Error Reporting....................................................................................... 117

3.7.5. Delayed Transactions and Data Parity Errors ....................................... 120

3.7.6. Error Recovery........................................................................................ 121

3.8. 64-B

XTENSION

................................................................................... 123

3.8.1. Determining Bus Width During System Initialization............................. 126

3.9. 64-

BIT

DDRESSING

......................................................................................... 127

3.10. S

PECIAL

ESIGN

ONSIDERATIONS

.............................................................. 130

4. ELECTRICAL SPECIFICATION...................................................................... 137

4.1. O

VERVIEW

....................................................................................................... 137

4.1.1. Transition Road Map .............................................................................. 137

4.1.2. Dynamic vs. Static Drive Specification ................................................... 138

4.2. C

OMPONENT

PECIFICATION

............................................................................ 139

4.2.1. 5V Signaling Environment ...................................................................... 140

4.2.2. 3.3V Signaling Environment ................................................................... 146

4.2.3. Timing Specification................................................................................ 150

4.2.4. Indeterminate Inputs and Metastability .................................................. 155

4.2.5. Vendor Provided Specification................................................................ 156

4.2.6. Pinout Recommendation ......................................................................... 157

PCI LOCAL BUS SPECIFICATION, REV. 3.0

4.3. S

YSTEM

OARD

PECIFICATION

....................................................................... 158

4.3.1. Clock Skew .............................................................................................. 158

4.3.2. Reset ........................................................................................................ 158

4.3.3. Pull-ups ................................................................................................... 161

4.3.4. Power ...................................................................................................... 163

4.3.5. System Timing Budget ............................................................................. 164

4.3.6. Physical Requirements ............................................................................ 167

4.3.7. Connector Pin Assignments .................................................................... 168

4.4. A

ARD

PECIFICATION

.......................................................................... 171

4.4.1. Add-in Card Pin Assignment................................................................... 171

4.4.2. Power Requirements ............................................................................... 176

4.4.3. Physical Requirements ............................................................................ 178

5. MECHANICAL SPECIFICATION.................................................................... 181

5.1. O

VERVIEW

....................................................................................................... 181

5.2. A

ARD

HYSICAL

IMENSIONS AND

OLERANCES

............................... 182

5.3. C

ONNECTOR

HYSICAL

ESCRIPTION

.............................................................. 195

5.4. C

ONNECTOR

HYSICAL

EQUIREMENTS

.......................................................... 205

5.5. C

ONNECTOR

ERFORMANCE

PECIFICATION

.................................................... 206

5.6. S

YSTEM

OARD

MPLEMENTATION

.................................................................. 207

6. CONFIGURATION SPACE .................................................................................. 213

6.1. C

ONFIGURATION

PACE

RGANIZATION

.......................................................... 213

6.2. C

ONFIGURATION

PACE

UNCTIONS

................................................................ 216

6.2.1. Device Identification ............................................................................... 216

6.2.2. Device Control ........................................................................................ 217

6.2.3. Device Status ........................................................................................... 219

6.2.4. Miscellaneous Registers.......................................................................... 221

6.2.5. Base Addresses........................................................................................ 224

6.3. PCI E

XPANSION

ROM

................................................................................... 228

6.4. V

ITAL

RODUCT

ATA

..................................................................................... 229

6.5. D

EVICE

RIVERS

.............................................................................................. 229

6.6. S

YSTEM

ESET

................................................................................................. 230

6.7. C

APABILITIES

IST

........................................................................................... 230

6.8. M

ESSAGE

IGNALED

NTERRUPTS

.................................................................... 231

6.8.1. MSI Capability Structure ........................................................................ 232

6.8.2. MSI-X Capability and Table Structures .................................................. 238

6.8.3. MSI and MSI-X Operation ...................................................................... 246

7. 66 MHZ PCI SPECIFICATION.......................................................................... 255

7.1. I

NTRODUCTION

................................................................................................. 255

7.2. S

COPE

............................................................................................................... 255

7.3. D

EVICE

MPLEMENTATION

ONSIDERATIONS

.................................................. 255

7.3.1. Configuration Space................................................................................ 255

7.4. A

GENT

RCHITECTURE

.................................................................................... 256

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