i.MX RT1050 Processor Reference
Manual
Document Number: IMXRT1050RM
Rev. 1, 03/2018
i.MX RT1050 Processor Reference Manual, Rev. 1, 03/2018
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Introduction
1.1 About This Document...................................................................................................................................................201
1.1.1 Audience...................................................................................................................................................... 201
1.1.2 Organization.................................................................................................................................................201
1.1.3 Suggested Reading.......................................................................................................................................201
1.1.3.1 General Information...................................................................................................................202
1.1.3.2 Related Documentation..............................................................................................................202
1.1.4 Conventions................................................................................................................................................. 202
1.1.5 Register Access............................................................................................................................................204
1.1.5.1 Register Diagram Field Access Type Legend............................................................................204
1.1.5.2 Register Macro Usage................................................................................................................204
1.1.6 Signal Conventions...................................................................................................................................... 206
1.1.7 Acronyms and Abbreviations.......................................................................................................................206
1.2 Introduction...................................................................................................................................................................209
1.2.1 Block Diagram............................................................................................................................................. 209
1.3 Features.........................................................................................................................................................................211
1.4 Target Applications.......................................................................................................................................................212
1.5 Endianness Support.......................................................................................................................................................213
Chapter 2
Memory Maps
2.1 Memory system overview.............................................................................................................................................215
2.2 ARM Platform Memory Map....................................................................................................................................... 215
Chapter 3
Interrupts, DMA Events, and XBAR Assignments
3.1 Overview.......................................................................................................................................................................223
3.2 CM7 interrupts..............................................................................................................................................................223
3.3 DMA Mux.....................................................................................................................................................................231
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Section number Title Page
3.4 XBAR Resource Assignments......................................................................................................................................239
Chapter 4
External Signals and Pin Multiplexing
4.1 Overview.......................................................................................................................................................................251
4.1.1 Muxing Options........................................................................................................................................... 251
Chapter 5
Fusemap
5.1 Boot Fusemap............................................................................................................................................................... 277
5.2 Lock Fusemap...............................................................................................................................................................288
5.3 Fusemap Descriptions Table.........................................................................................................................................288
Chapter 6
External Memory Controllers
6.1 Overview.......................................................................................................................................................................303
6.2 Smart External Memory Controller (SEMC) Overview...............................................................................................303
6.3 eMMC/eSD/SDIO.........................................................................................................................................................305
6.4 Quad Serial Peripheral Interface...................................................................................................................................306
Chapter 7
System Debug
7.1 Overview.......................................................................................................................................................................307
7.2 Chip and ARM Platform Debug Architecture.............................................................................................................. 307
7.2.1 Debug Features............................................................................................................................................ 308
7.2.2 Debug system components...........................................................................................................................308
7.2.2.1 AMBA Trace Bus (ATB)...........................................................................................................308
7.2.2.2 CoreSight trace port interface (TPIU)........................................................................................309
7.2.2.3 Embedded Trace Macrocell (ETM)........................................................................................... 310
7.2.2.4 Instrumentation Trace Macrocell...............................................................................................310
7.2.3 Chip-Specific SJC Features......................................................................................................................... 311
7.2.3.1 JTAG Disable Mode.................................................................................................................. 311
7.2.3.2 JTAG ID.....................................................................................................................................311
7.2.4 System JTAG controller main features........................................................................................................312
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Section number Title Page
7.2.5 SJC TAP Port...............................................................................................................................................312
7.2.6 SJC main blocks...........................................................................................................................................312
7.3 Miscellaneous............................................................................................................................................................... 313
7.3.1 Clock/Reset/Power.......................................................................................................................................313
7.4 Supported tools............................................................................................................................................................. 313
Chapter 8
System Boot
8.1 Chip-specific Boot Information.................................................................................................................................... 315
8.2 Overview.......................................................................................................................................................................318
8.3 Boot modes................................................................................................................................................................... 319
8.3.1 Boot mode pin settings.................................................................................................................................320
8.3.2 High-level boot sequence.............................................................................................................................320
8.3.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)..................................................................................321
8.3.4 Serial Downloader (BOOT_MODE[1:0] = 01b)......................................................................................... 322
8.3.5 Internal Boot mode (BOOT_MODE[1:0] = 0b10)...................................................................................... 322
8.3.6 Boot security settings...................................................................................................................................323
8.4 Device configuration.....................................................................................................................................................324
8.4.1 Boot eFUSE descriptions.............................................................................................................................324
8.4.2 GPIO boot overrides.................................................................................................................................... 325
8.4.3 Device Configuration Data (DCD).............................................................................................................. 326
8.5 Device initialization......................................................................................................................................................326
8.5.1 Internal ROM/RAM memory map...............................................................................................................327
8.5.2 Boot block activation .................................................................................................................................. 327
8.5.3 Clocks at boot time...................................................................................................................................... 328
8.5.4 Enabling Caches...........................................................................................................................................330
8.5.5 Exception handling...................................................................................................................................... 330
8.5.6 Interrupt handling during boot..................................................................................................................... 331
8.5.7 Persistent bits............................................................................................................................................... 331
8.6 Boot devices (internal boot)..........................................................................................................................................331
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