基于 FPGA 的 I2C 总线模拟，采用 Verilog HDL 语言编写
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2020-05-08
12:35:06
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I2C_Verilog.zip （68个子文件） 
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hdllib.ref 231B vlg5C i2c_master_byte_ctrl.bin 19KB vlg07 i2c_master_bit_ctrl.bin 30KB vlg67 i2c_master_top.bin 18KB prjname.lso 6B i2c_master_top.v 6KB i2c_slave_model.udo 204B coregen.log 705B __projnav.log 31KB i2c_master_bit_ctrl.v 13KB I2C.dhp 5KB i2c_master_bit_ctrl.stx 765B timescale.v 23B wb_master_model.v.bak 5KB i2c_master_byte_ctrl.ngr 92KB i2c_slave_model.v 8KB i2c_master_bit_ctrl.syr 14KB work i2c_slave_model verilog.asm 35KB _primary.vhd 492B _primary.dat 4KB _info 322B glbl verilog.asm 4KB _primary.vhd 172B _primary.dat 528B i2c_master_bit_ctrl.v.bak 16KB i2c_master_byte_ctrl.v.bak 10KB i2c_master_top.stx 2KB transcript 755B i2c_master_bit_ctrl.prj 36B i2c_master_bit_ctrl.lso 6B i2c_master_bit_ctrl.cmd_log 87B i2c_master_byte_ctrl.syr 18KB coregen.prj 7KB i2c_slave_model.fdo 386B i2c_master_top.lso 6B automake.log 0B wb_master_model.v 3KB i2c_master_byte_ctrl.stx 1KB i2c_master_top.cmd_log 77B i2c_master_byte_ctrl.v 7KB i2c_master_top.v.bak 10KB i2c_slave_model.ndo 428B i2c_master_defines.v.bak 3KB i2c_master_defines.v 214B i2c_master_top.syr 20KB i2c_master_byte_ctrl.ngc 52KB I2C.npl 919B i2c_master_top.ngc 81KB i2c_master_bit_ctrl.ngr 46KB __projnav runXst_tcl.rsp 91B i2c_master_byte_ctrl.xst 1020B xst_sprjTOstx_tcl.rsp 72B coregen.rsp 111B I2C_flowplus.gfl 805B I2C.gfl 2KB i2c_master_bit_ctrl.xst 1016B i2c_master_top.xst 996B i2c_master_top.ngr 120KB i2c_master_top.prj 104B tst_bench_top.v 9KB i2c_slave_model.v.bak 11KB i2c_master_byte_ctrl_vhdl.prj 0B i2c_master_byte_ctrl.cmd_log 89B i2c_master_byte_ctrl.lso 6B i2c_master_bit_ctrl_vhdl.prj 0B i2c_master_bit_ctrl.ngc 31KB i2c_master_top_vhdl.prj 0B i2c_master_byte_ctrl.prj 73B资源评论
