ug472_7Series_Clocking.pdf

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关于xilinx Virtex-7 时钟资源的技术文档,介绍了关于七系列的时钟结构,例一个时钟的具体时钟构造,列举的各种时钟buffers,时钟如何被驱动。
Revision History The following table shows the revision history for this document Date Version Revision 03/01/2011 1.0 Initial Xilinx release 03/28/2011 1.1 Updated disclaimer and copyright on page 2. Updated Clocking Architecture Overview and Figure 2-2. Revised the discussion in Clock-Capable Inputs including adding Table 1-1 and Figure 2-1. Revised some of the global Clock Buffers descriptions. Revised the description under Figure 2-17. Updated the I/o Clock Buffer--BUFIO section Updated Figure 2-20. Updated the Regional clock Buffer--BUFR section Updated the description in Table 2-8. Revised Figure 2-23 Added the BuFmrCe to the BUFMR Primitive section including Figure 2-25. Added BUFHCE to the Horizontal Clock Buffer--BUFH, BUFHCE section Moved Clock Gating for Power Savings Updated the MMCMs and PLLs section. Revised the Frequency Synthesis Only Using Integer Divide section including Figure 3-4. Revised the discussion around adjacent regions in ClKOUT[O: 6]-Output Clocks Updated the examples after Equation 3-11 Moved and revised VHDL and Verilog Templates and the Clocking Wizard Added Appendix A, Multi-Region Clocking 05/31/20111.2 Added section on 7 Series FPGAs Clocking Differences from Previous FPGA Generations Updated Figure 2-2. Clarified discussion in Clock-Capable Inputs section including removing table 1-1: Migration of devices in the same package with different top/bottom alignments. Redrew Figure 2-4, Figure 2-16, Figure 2-18, and Figure 2-22 Updated description of CLKOUT[0: 6]in Table 3-5. Updated CLKFBSTOPPED Feedback Clock Status, page 83 Clarified the MMCM,PLL relationship including updating Figure 3-10 Added more information to the Phase Shift section, including Equation 3-5 Revised Figure A-6 and Figure A-7. Added Appendix B, Clocking Resources and Connectivity Variations per Clock Region 10/27/2011 1.3 Moved 7 Series FPGAs Clocking Differences from Previous FPGA Generations. Added Clock Buffer Selection Considerations. Clarified description in Clock-Capable Inputs Added another note after Figure 2-22, page 53. Added the Stacked Silicon Interconnect Clocking section Updated Figure 3-6, page 73 Clarified descriptions in Frequency Synthesis Using Fractional Divide in the MMCM, page 73, Interpolated Fine Phase Shift in Fixed Dynamic Mode in the MMCM, page 75, Determine the Input Frequency, page 76, CLKOUT[O: 6]-Output Clocks, page 82, and Reference Clock Switching, page 91 Revised description of STARTUP_WAIT, page 85. Updated rst description in Table 3-5, page 78. Updated CLKOUT[O]DIVIDE_F(2)allowed values in Table 3-7, page 83 Updated Clock Network Deskew, page 72 adding Figure 3-12, page 92 Updated Table B-1 and added Table B-2 02/16/2012 1.4 Replaced"clocking backbone"with"clock backbone" and"clocking region"with"clock region"throughout Added Chapter 1, Clocking Overview, containing 7 Series FPGAs Clocking Differences from Previous FPGa Generations from Chapter 2 and Summary of Clock Connectivity from Appendix B Updated Table 1-1. Removed XC7A8, XC7A15, XC7A30T, and XCA50T from Table 1-2 Added Clock-Capable Inputs Updated Global Clocking Resources including buFmr Primitive Updated Horizontal Clock Buffer--BUFH, BUFHCE Updated paragraph before Figure 2-27. UG472(114)Jy30.2018 www.xilinx.com7SeriesFpgaSClockingResourcesUserGuide Date Version Revision 02/16/2012 1.4 In introductory paragraph of High-Performance Clocks, removed description of HPCs (Contd) connecting to OSERDES and buffers. Replaced cross reference to UG429, 7 Series FPGAs Migration Methodology guide, with UG872, Large FPGA Methodology Guide. Updated Stacked Silicon Interconnect Clocking Replaced SRL with SLR in Figure 2-29 Added Figure 2-31 Removed hold block from Figure 3-2. Updated clock frequencies in Frequency Synthesis Only Using Integer Divide Replaced 64 with 63 in Equation 3-4. Updated Interpolated Fine Phase shift in Fixed or Dynamic Mode in the MMCM. Updated pin description of LOCKED in Table 3-5. Updated LOCKED In Table 3-7, updated type and allowed values of ClKoUt[O -DIVidE- F and CLKFBOUT_ MULT_F, and description of STARTUP WAIT and COMPENSATION. In Table 3-8, added STARTUP WAIT and updated description of COMPENSATION. Replaced GTX with GTin Figure 3-10 Updated Dynamic Reconfiguration Port Added Appendix B, Clocking Resources and Connectivity Variations per Clock Region 07/13/2012 1.5 Updated paragraph after Figure 1-4. Added bullet about spread spectrum support to Key Differences from Virtex-6 FPGAs. Updated BUFG and BUFH pins and removed IBUFDS--GTE2.O/IBUFDS-GTE2ODIV2 pin from Table 1-1. Updated Table 1-2 Updated note 5 in Table 2-1. Added Figure 2-29 Updated last sentence of Introduction. Updated Do[15: 0]-Dynamic reconfiguration Output Bus. Added Ss_EN, SS_MODE, and Ss_MOD- PERiOd to Table 3-7. Added Spread-Spectrum Clock Generation 10/02/2012 1.6 Added note to table 1-1. Removed xc7a350T and XCV1500T from Table 1-2 Updated first paragraph of single clock driving multiple cmts. added notes 5 and 8 to Tablc 2-1. Updated paragraph after Tablc 2-10 Added Table 3-9 and timing constraint calculations for 25 MHz and 80 MHz input clocks In Table 3-10, changed Bandwidth value from N/A to Low, and removed duplicate paragraph after table Removed XC7A350T from title of Figure B-4 04/03/2013 1.7 Updated Figure 1-3, Figure B-2, and Figure B-3. Added BUFMR to Table 1-1. Updated second paragraph in Dynamic Phase Shift Interface in the MMCM. Added note to Table 2-7 08/07/2013 1.8 Updated Table 1-2 and Table 3-7. Updated the figure titles for Figure B-2 and Figure B-3 Updated Clock Buffer Placement 04/08/2014 1.9 Updated Clock-Capable Inputs and Dynamic Phase Shift Interface in the MMCM Updated allowed values and the default value for ClKFBOUT MULt in Table 3-8 05/24/2014 1.10 Changed the value of minimum clock regions from six to four in Clocking Architecture Overview. Added information to mgtreFClKo in Table 1-1. Added section on gtZ Loopback Clock Buffer- BUFG- LB(HT devices only)to Chapter 2 Changed description of reF- JITTErl and ref JITTER2 in Table 3-7 and Table 3-8. Updated first paragraph in Use Cases 11/19/2014 Removed general interconnect from this bulleted list on page 49. Updated the figure titles for Figure B-2 and Figure B-3 03/04/2015 1.11.1 Updated Frequency Synthesis Using Fractional Divide in the MMCm, page 73 by changing 0.125 degrees to 0.125 06/12/2015 1.11.2 Fixed broken link in three references to 7 Series FPGA Data Sheets on page 73 and page 74 09/27/2016 1.12 Added the Spartan-7 FPGAS and the artix-7 (XC7 A12T and XC7 A25T)devices where applicable including updating Appendix B Updated the BUFR Alignment section Updated the Automotive Applications Disclaimer 7seRiesFpgasclockingResourcesUserGuidewww.xilinx.com UG472(114)山uy30,2018 Date Version Revision 03/01/2017 1.13 Updated the bufr alignment section 07/30/2018 1.14 Updated the example in Determine the Input Frequency section UG472(114)Jy30.2018 www.xilinx.com7SeriesFpgaSClockingResourcesUserGuide 7seRiesFpgasclockingResourcesUserGuidewww.xilinx.com UG472(114)山uy30,2018 Table of Contents Revision history Preface: About This Guide Guide Contents Additional resources Chapter 1: Clocking Overview Clocking Architecture Overview 13 Clock Routing resources overview,…… 13 CMT Overview∴ 14 Clock Buffers, Management, and routing 15 7 Series FPGAs Clocking Differences from Previous FPGA Generations...21 Key Differences from Virtex-6 FPGAs Key Differences from Spartan-6 FPGAs Summary of Clock Connectivity.……… 24 Clocking Differences in 7 Series TPGA 27 Chapter 2: Clock Routing Resources Clock Buffer Selection Considerations Clock-Capable Inputs 30 Single clock driving a single cmt Single Clock Driving Multiple Cmts Clock-Capable Input pin placement rules 31 Global Clocking Resources ....35 Clock tree and Nets -GCLK ..36 Clock regions 36 Global Clock buffers ....,,36 Global Clock buffer primitives 38 Additional Use Models Regional Clocking resources 48 Clock-Capable [/ o 49 I/O Clock Buffer--BUFIO 49 BUFIO Primitive .50 BUFIO USe models 50 Regional clock buffer--BUFR 52 BUFR Primitive.....,,,,,,,,,,,,,,, ...52 BUFR Attributes and modes 53 BUFR USe models Regional Clock nets∴… 54 Multi-Region Clock Buffer--BUFMR/ BUFMRCE 55 BUFMR Primitive Horizontal clock buffer—BUFH, BUFHCE........….…..57 GTZ Loopback Clock buffer- BUFG LB( hT devices only).…………58 High-Performance Clocks ....59 7SeriesFpgaSclockingResourcesUserGuidewww.xilinx.com Send feedback UG472(1.14)Juy30.2018 &A XILINX Clock Gating for power savings Stacked silicon interconnect clockin g Placement of Clocking Structures……… 62 Clock Buffer placement ··· ,,,,,,63 Chapter 3: Clock Management Tile Introduction MMCMS and plls .66 General Usage Description MMCM and pi primitives MMCME2 BASE and PLLE2 BASE Primitives MMCME2 ADV and PllE2 ADV Primitive 71 Clock Network deskew 72 Frequency Synthesis Only Using Integer Divide Frequency Synthesis Using Fractional Divide in the MMCM........... 73 Jitter Filter 73 Limitations vCO Operating range :·····: 73 Minimum and maximum Input frequency Duty Cycle programmability Phase Shift 74 Dynamic phase shift Interface in the mmcm MMCM Counter Cascading 76 MMCM/PLL Programming 76 Determine the Input frequency.…∴…… 76 Determine the m and d values 77 MMCM Ports ..78 PLL Ports MMCM and Pll Port Descriptions MMCM Attributes PLL Attributes ..87 MMCM Clock Input Signals ..89 Counter Control 8 Detailed Vco and Output Counter Waveforms Reference Clock Switching ···· Missing Input Clock or Feedback Clock MMCM and pll use models ..91 Clock network deskew MMCM with Internal Feedback ..93 Zero delay buffer CMT to CMr Connection 94 Spread-Spectrum Clock Generation MMCM APPlication Example ...101 Dynamic Reconfiguration Port l01 VHDL and verilog Templates and the Clocking wizard Appendix A: Multi-Region Clocking Introduction Clocking Across Multiple Regions BUFMR Primitive 104 Send feedback www.xilinx.com7SeriesFpgaSClockingResourcesUserGuide UG472(V114)Jy30,2018 S XILINX Use Cases 105 Clock alignment across clock regions .,106 Single buffe g Clock regi Driving Multiple BUFIOs 106 Drit Multiple burrs Multiple buffers per Clock region 107 Driving Multiple burrs(with Divide) and BUFIO 107 Driving Multiple bUFRs (With and Without Divide BUFR Alignment ,110 Appendix B: Clocking Resources and Connectivity Variations per Clock Region 7SeriesFpgaSClockingResourcesUserGuidewww.xilinx.com Send feedback UG472(1.14)Juy30.2018 &A XILINX 10 Send feedback www.xilinx.com7SeriesFpgaSClockingResourcesUserGuide UG472(V114)Jy30,2018

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