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Spartan-6 FPGA

Block RAM

Resources

User Guide

UG383 (v1.3) October 13, 2010

Spartan-6 FPGA Block RAM www.xilinx.com UG383 (v1.3) October 13, 2010

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,

without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves

the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors

contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with

technical support or assistance that may be provided to you in connection with the Information.

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Revision History

The following table shows the revision history for this document.

Date Version Revision

06/24/09 1.0 Initial Xilinx release.

10/29/09 1.1 Added last bullet to Asynchronous Clocking discussion. Revised the Unused Inputs

connection to Low.

02/23/10 1.2 Changed the Possible Configurations section which includes removal of the 9 Kb block

RAM (simple dual-port operation) section. Additional changes throughout the

document involve removal of this information. Added port names to

Table 2 through

Table 3

. Updated Asynchronous Clocking discussion. Changed Data and Address

Width - DATA_WIDTH_A, DATA_WIDTH_B. Updated Figure 14.

10/13/10 1.3 Clarification edits to the Asynchronous Clocking, page 15 description. Added Block

RAM Access Through the Configuration Port design consideration.

Spartan-6 FPGA Block RAM www.xilinx.com 3

UG383 (v1.3) October 13, 2010

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Block RAM Resources

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Possible Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

9 Kb Block RAM—Simple Dual-Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

9 Kb Block RAM—True Dual-Port Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

18 Kb Block RAM—True Dual-Port Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Spartan-6 FPGA Block RAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Spartan-6 FPGA Block RAM Usage Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Synchronous Dual-Port and Simple Dual-Port RAMs . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

WRITE_FIRST or Transparent Mode (Default). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

READ_FIRST or Read-Before-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

NO_CHANGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Conflict Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Synchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Optional Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Simple Dual-Port Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Byte-wide Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block RAM Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block RAM Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Clock - CLKA, CLKB (CLKAWRCLK, CLKBRDCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Enable - ENA, ENB (ENAWREN, ENBRDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Byte-wide Write Enable - WEA, WEB (WEAWEL, WEBWEU) . . . . . . . . . . . . . . . . . . 20

Set/Reset - RSTA, RSTB (RSTA, RSTBRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Address Bus - ADDRA, ADDRB (ADDRAWRADDR, ADDRBRDADDR) . . . . . . . . 21

Data-In Buses - DIA, DIB (DIADI, DIBDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Data-In Parity - DIPA, DIPB (DIPADIP, DIPBDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Data-Out Buses - DOA, DOB (DOADO, DOBDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Data-Out Parity - DOPA, DOPB (DOPADOP, DOPBDOP) . . . . . . . . . . . . . . . . . . . . . 22

GSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block RAM Address Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block RAM Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data and Address Width - DATA_WIDTH_A, DATA_WIDTH_B . . . . . . . . . . . . . . . 23

Table of Contents

4 www.xilinx.com Spartan-6 FPGA Block RAM

UG383 (v1.3) October 13, 2010

Content Initialization - INIT_xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Content Initialization - INITP_xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Output Latches Initialization - INIT_A, INIT_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Output Latches/Registers Synchronous Set/Reset - SRVAL_A, SRVAL_B . . . . . . . . 24

RAM MODE - RAM_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset or CE Priority - RST_PRIORITY_A, RST_PRIORITY_B. . . . . . . . . . . . . . . . . . . . 25

Data Latch Reset - EN_RSTRAM_A, EN_RSTRAM_B . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reset Type - RSTTYPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Optional Output Register On/Off Switch - DO[A|B]_REG . . . . . . . . . . . . . . . . . . . . . 26

Write Mode - WRITE MODE_A, WRITE_MODE_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Block RAM Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Block RAM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Additional Block RAM Primitive Design Considerations . . . . . . . . . . . . . . . . . . . . 26

Optional Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

RAMB16BWER and RAMB8BWER Port Mapping Design Rules. . . . . . . . . . . . . . . . . 27

Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Byte-wide Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Block RAM Access Through the Configuration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Block RAM Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Creating Larger RAM Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Block RAM RST in Register Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Block RAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Block RAM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Block RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Clock Event 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Clock Event 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock Event 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clock Event 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Block RAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

剩余33页未读，继续阅读

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