Whitley_PDG574174_r0_61资源-CSDN文库

4星 · 超过85%的资源需积分: 26 23 浏览量 2019-04-22 16:00:08 上传评论 3 收藏 16.4MB PDF 举报

资源推荐

资源详情

资源评论

Reference Number: 574174

Whitley Platform

Design Guide

Revision 0.61

February 2018

Intel Confidential

2 Reference Number: 574174, Revision: 0.61

Intel Confidential

Legal Lines and Disclaimers

Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service

activation. Learn more at Intel.com, or from the OEM or retailer.

No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any

damages resulting from such losses.

You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel

products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted

which includes subject matter disclosed herein.

No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.

The products described may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

This document contains information on products, services and/or processes in development. All information provided here is

subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps.

Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for

a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or

usage in trade.

Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-

4725 or by visiting www.intel.com/design/literature.htm.

Intel, Xeon, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.

*Other names and brands may be claimed as the property of others.

Notice: This document contains information on products in the design phase of development. The information here is subject to

change without notice. Do not finalize a design with this information.

Reference Number: 574174, Revision: 0.61 3

Intel Confidential

Contents

1 Introduction and Overview......................................................................................39

1.1 Whitley Overview .............................................................................................. 39

1.2 Document Scope / PDG Disclaimer....................................................................... 43

1.3 Routing Guideline Table Terminology Definition ..................................................... 43

1.4 Component Quadrant Layouts.............................................................................45

1.4.1 Icelake Server 2S with 2 Intel® Ultra Path Interconnect

(Intel® UPI) Quadrant Layout..................................................................45

1.4.2 Lewisburg Quadrant Layout .....................................................................46

1.5 Server Select Solutions......................................................................................47

2 PCB Design Guidelines............................................................................................. 49

2.1 PCB Stackup Modeling........................................................................................49

2.1.1 Dielectric Material and Copper Properties...................................................49

2.1.2 PCB Impedance Tolerance and Insertion Loss Maximum .............................. 50

2.2 PCB Stackup References.....................................................................................53

2.2.1 0.075 inch 12-Layer Stackup ................................................................... 53

2.2.2 0.086 inch 16-Layer Stackup ................................................................... 54

2.3 Insertion Loss Verification .................................................................................. 55

2.3.1 Via Effects on Insertion Loss Measurements............................................... 55

2.4 Environmental Effects on Insertion Loss ...............................................................55

3 General High Speed Guidelines................................................................................ 57

3.1 Length Matching Requirements ........................................................................... 58

3.2 Serpentine Routing Rule.....................................................................................64

3.3 Routing Clearance from Anti-Pad.........................................................................65

3.4 Controlling Voltage Regulator VR Noise ................................................................65

3.4.1 Example of Problematic Design That Should Be Avoided .............................. 67

3.5 educing High Frequency Noise on Voltage Regulator Planes.....................................70

3.6 Reference Plane ................................................................................................ 71

3.7 Trace Corners................................................................................................... 74

3.8 Escape Routing .................................................................................................74

3.9 Routing Through a Pin Field ................................................................................81

3.10 Layer Transitions and Via Stubs...........................................................................83

3.11 Connector Routing Guideline...............................................................................91

3.12 Routing Under Connector Footprint...................................................................... 93

3.13 High Speed Lane Reversal and Polarity Inversion...................................................95

3.14 DC Blocking Cap Design Pad ...............................................................................96

3.15 DC Blocking Cap Ground Voiding .........................................................................97

3.16 Fiberweave effect mitigation ...............................................................................98

3.17 Treatment of RSVD pins.....................................................................................99

3.18 Dual Stripline Routing Guidelines.........................................................................99

3.19 Intel UPI Dual Stripline Routing Guidelines.......................................................... 101

3.19.1 For 10-Layer 93-mil Dual-Stripline Stackup.............................................. 101

3.19.2 For Half-Width 12-Layer 72-mil Dual-Stripline Stackup.............................. 102

3.20 Crosstalk Considerations due to Signal Polarity.................................................... 102

3.21 Recessed Ground Plane for Edge Card Connector................................................. 104

3.22 High-speed Crosstalk Control for Edge Connector ................................................ 105

4 Platform Clocking .................................................................................................. 107

4.1 Clocking Architectures...................................................................................... 108

4.1.1 Native Integrated System Clocking (isCLK) Architecture ............................ 108

4.1.2 Platform Hybrid Clocking Architecture ..................................................... 110

4.1.3 External Clocking (ExtClk) Architecture ................................................... 112

4.2 Clocking Design Guidelines ............................................................................... 116

4 Reference Number: 574174, Revision: 0.61

Intel Confidential

4.2.1 Differential Clocks.................................................................................116

4.2.2 Single-Ended Clocks..............................................................................142

4.3 Other Clocking Considerations ...........................................................................148

4.3.1 Clock Driver Decoupling and Clock Power Delivery.....................................148

4.3.2 EMI Constraints....................................................................................150

4.3.3 Crystal / Oscillator Recommendations and Guidelines ................................150

5 Intel® Ultra Path Interconnect (Intel® UPI)..........................................................161

5.1 Intel® Ultra Path Interconnect (Intel® UPI) Physical Layer Connectivity .................161

5.2 Intel® Ultra Path Interconnect (Intel® UPI) Signal List and Description of Functions.162

5.3 Intel® Ultra Path Interconnect (Intel® UPI) Layout Topologies ..............................162

5.3.1 Intel® Ultra Path Interconnect (Intel® UPI) Internal Layer Topology 1 ........164

5.3.2 Intel® Ultra Path Interconnect (Intel® UPI) External

Layer Routing Topology 2 ......................................................................167

5.3.3 Intel® Ultra Path Interconnect (Intel® UPI) External

Layer Breakouts with Internal Layer Routing Topology 3 ............................169

5.3.4 Intel UPI External Layer Breakout Topology 4 on One

Side with Internal Layer Routing.............................................................171

5.3.5 Intel UPI Internal Layer 1-Connector Topology 5.......................................173

5.3.6 Intel® UPI Internal Layer 2-Conn Topology 6 ...........................................174

5.3.7 Intel® UPI Internal Layer 2-Conn Cable Topology 7...................................176

5.4 Intel® Ultra Path Interconnect (Intel® UPI) General Routing Guidelines..................177

6 Processor Miscellaneous Signals Guidelines...........................................................181

6.1 Processor Miscellaneous Signals Routing Guidelines..............................................182

6.2 CATERR_N, MSMI_N, TSC_SYNC and PM_FAST_WAKE_N Routing Guidelines ...........190

6.2.1 CATERR_N, MSMI_N, TSC_SYNC and PM_FAST_WAKE_N Topologies............192

6.3 PMSYNC & PMSYNC_CLK Routing Guidelines........................................................222

6.4 Processor Identification Routing Guidelines..........................................................226

6.5 PROCHOT_N Routing Guidelines.........................................................................229

6.5.1 PROCHOT_N Topologies.........................................................................230

6.6 ERROR[2:0]_N, FIVR_FAULT, THERMTRIP_N, MEMTRIP_N and

MEMHOT_IN/OUT_N Routing Guidelines..............................................................239

6.7 PWRGOOD, RESET_N, and MEMHOT_IN_N Routing Guidelines ...............................250

6.7.1 PWRGOOD, RESET_N, and MEMHOT_IN_N Topologies ...............................250

6.8 SMBus Routing Guidelines.................................................................................252

6.8.1 DDR_SPDSCL and PE_HP_SCL to Voltage Translator..................................254

6.8.2 Calculating the SMBus Physical Segment Pull-up Resistor...........................266

6.9 SVID Routing Guidelines...................................................................................266

6.9.1 SVID Topologies...................................................................................267

6.10 Boot Mode Straps ............................................................................................273

6.11 DDR_DRAM_PWR_OK Routing Guidelines............................................................275

6.12 Platform Firmware Resilience (PFR) Routing Guidelines .........................................278

7 DDR4/DDR-T Memory Routing Guidelines ..............................................................287

7.1 Scaling of Maximum topology Lengths to accommodate a higher

PCB Loss than Mid-loss.....................................................................................287

7.2 Scaling of Maximum topology Lengths to accommodate a higher

PCB Loss than Low-loss ....................................................................................287

7.3 DIMM Connector Layout Design Considerations....................................................287

7.4 Stackup and Reference Plane Guidelines .............................................................288

7.4.1 Voltage Plane Reference Signal Routing Guidelines....................................288

7.4.2 Routing Guidelines Around VRs and Other High Noise Sources ....................289

7.5 System Level DIMM Population Requirements......................................................289

7.6 DDR4 Only Socket Level Population Requirements................................................290

7.7 DDR4 and BPS Socket Level Population Requirements...........................................293

7.8 Channel Level DIMM Population Requirements.....................................................296

7.8.1 General Population Requirements............................................................296

Reference Number: 574174, Revision: 0.61 5

Intel Confidential

7.9 Two Slots per Channel DIMM Population Requirements......................................... 297

7.10 One Slot per Channel DIMM Population Requirements .......................................... 297

7.11 DIMM SPD Addressing Requirements.................................................................. 298

7.12 Memory RAS Feature Support vs DIMM Population............................................... 299

7.13 DDR4/DDR-T Design Considerations .................................................................. 300

7.13.1 DDR4/DDR-T Signal Groupings............................................................... 300

7.13.2 DDR4/DDR-T Data Strobe (DQS) to Data (DQ_ECC) Affinity....................... 301

7.13.3 DDR4/DDR-T Control Connectivity .......................................................... 302

7.13.4 DDR4/DDR-T Clock to Command, Control and Address Signal Association .... 303

7.13.5 DDR4/DDR-T 2SPC DIMM Population Configurations.................................. 303

7.13.6 DDR4/DDR-T 1SPC DIMM Population Configurations.................................. 304

7.13.7 DDR4/DDR-T Processor Control/Clock Signal to DIMM Pin Connections ........ 305

7.14 DDR4/DDR-T Design Topologies and Guidelines................................................... 306

7.15 DDR4/DDR-T Required Layout Techniques.......................................................... 306

7.16 DDR4/DDR-T Two DIMM Slot Per Channel Guidelines with

PTH Connectors (LRDIMM/RDIMM/BPS DIMMs).................................................... 312

7.16.1 DDR4/DDR-T Source-Synchronous Signal Guidelines,

2SPC - DQ[63:00], DQS_{DP/DN}[17:00], ECC[7:0]................................ 312

7.16.2 DDR4/DDR-T Source Clocked Signal Guidelines,

2SPC - MA[17,13:00],BA[1:0], BG[1:0], RAS_N/MA[16],

CAS_N/ MA[15],CID[2], WE_N/MA[14], PAR, and ACT_N........................... 317

7.16.3 DDR4/DDR-T Source Clocked Signal Guidelines, 2SPC -

CS_N[7:0], ODT[3:0], and CKE[3:0] ...................................................... 320

7.16.4 DDR4/DDR-T Clock Signal Guidelines, 2SPC - CLK_{DP/DN} [3:0].............. 323

7.17 DDR4/DDR-T One DIMM Slot Per Channel Guidelines with

PTH Connectors (LRDIMM / RDIMM / BPS DIMM) ................................................. 326

7.17.1 DDR4/DDR-T Source-Synchronous Signal Guidelines,

1SPC - DQ[63:00], DQS_{DP/DN}[17:00], ECC[7:0]................................ 326

7.17.2 DDR4/DDR-T Source Clocked Signal Guidelines,

1SPC - MA[17,13:00], BG[1:0], CID[2],BA[1:0],

RAS_N/MA[16], CAS_N/MA[15], WE_N/MA[14],

PAR, and ACT_N................................................................................... 330

7.17.3 DDR4/DDR-T Source Clocked Signal Guidelines,

1SPC - CS_N[3:0],ODT[1:0]and CKE[1:0]............................................... 332

7.17.4 DDR4/DDR-T Clock Signal Guidelines, 1SPC - CLK_{DP/DN} [0/1].............. 333

7.18 DDR4/DDR-T with SMT Connector Guidelines (LRDIMM/RDIMM/BPS DIMMs) ........... 335

7.18.1 Single DIMM via Transition SMT Connector Design Guideline ...................... 335

7.18.2 DDR4/DDR-T Source-Synchronous Signal Guidelines,

2SPC DQ[63:00], DQS_{DP/DN}[17:00], ECC[7:0].................................. 339

7.18.3 DDR4/DDR-T Source Clocked Signal Guidelines,

2SPC MA[17,13:00],BA[1:0], BG[1:0], RAS_N/MA[16],

CAS_N/ MA[15],CID[2], WE_N/MA[14], PAR, and ACT_N........................... 345

7.18.4 DDR4/DDR-T Source Clocked Signal Guidelines,

2SPC CS_N[7:0], ODT[3:0], and CKE[3:0] .............................................. 349

7.18.5 DDR4/DDR-T Clock Signal Guidelines, 2SPC - CLK_{DP/DN} [3:0].............. 353

7.19 DDR4/DDR-T Length Matching Requirements ...................................................... 356

7.20 DDR4/DDR-T Interface Common Requirements ................................................... 356

7.21 DDR4 Miscellaneous Signal Guidelines................................................................ 357

7.21.1 DDR4 Test Signals Guidelines................................................................. 357

7.21.2 DDR4 SPD Signal Guidelines .................................................................. 358

7.21.3 DDR4 DIMM Reference Voltage Guidelines ............................................... 358

7.21.4 DDR4 Alert Signal Guidelines ................................................................. 360

7.21.5 DDR4 DRAM Reset Signal Guidelines....................................................... 364

7.21.6 DDR4 DRAM Power OK Topologies and Guidelines..................................... 368

7.21.7 Memory Hot Signal Guidelines................................................................ 368

8 Processor IO Interface Guidelines ......................................................................... 369

8.1 PCIe* Layout Design Guidelines ........................................................................ 369

剩余1033页未读，继续阅读

评论收藏

内容反馈

qq_38994797

2020-05-08

WHITLEY平台的白皮书

weixin_43264483

粉丝: 1
资源: 1

Whitley_PDG574174_r0_61

Intel_Romley_PDG_1.1

服务器基础知识大全汇编.pdf

Intel微处理器结构、编程与接口（pdg格式）

544924_intel skylake平台EDS_CPU规格书

Inter 官网手册

A_Genetic_Algorithm_Tutorial.Darrell_Whitley.[EN]

RecyclerView添加EmptyView

Android MD控件之CardView

Android之Fragment的基本使用

Intel Skylake Platform Power Architecture Guide

High Speed USB Platform Design Guidelines_pdg_r1_0.pdf

Wholesale Price Contract with Retailer\'s Fairness Concerns

解决any change made in its configuration may be lost after reimport

Intel 下一代 处理器开发文档

关于Fragment重叠问题分析和解决

Listview中完美嵌套HorizontalListView

Android自定义控件之购物车数量加减器

notifyDataSetChanged失效的原因总结

Android24.2.0支持库中的SnapHelper学习和使用

intel处理器检测

561280_KBL_UY_PDG_Rev2p1

Android界面之几种常用的自定义Dialog

Android仿QQ讨论组组合头像

listView嵌套横向listView

MATLAB用拟合出的代码绘图-septal_constriction_analysis:包含用于拟合间隔图像并分析收缩与时间数据的功能

A Genetic Algorithm Tutorial.pdf

Genetic Algorithms and Evolutionary Computing.pdf

基于5种大型底栖动物评价指数的河流生态健康评价 (2017年)

final-project-abbottwhitley:由GitHub Classroom创建的final-project-abbottwhitley

最新资源

Intel 下一代处理器开发文档