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FPGA设计数字钟
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2018-10-31
20:37:04
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FPGA设计数字钟 （182个子文件） 
elaborate.bat 917B compile.bat 840B simulate.bat 807B runme.bat 229B runme.bat 229B clk_display.bit 2.09MB clk_display_behav_6472_1540696215.btree 0B xsim_1.c 5KB xsim.dbg 10KB clk_display_routed.dcp 212KB clk_display_placed.dcp 186KB clk_display_opt.dcp 155KB clk_display.dcp 47KB
xsimk.exe 76KB
usage_statistics_webtalk.html 31KB usage_statistics_ext_xsim.html 3KB .xsim_webtallk.info 64B xsimSettings.ini 735B xsim.ini 40B webtalk.jou 1KB webtalk_12132.backup.jou 1KB vivado.jou 830B vivado.jou 826B ISEWrap.js 7KB ISEWrap.js 7KB rundef.js 1KB rundef.js 1KB runme.log 32KB runme.log 27KB webtalk_12132.backup.log 2KB webtalk.log 1KB elaborate.log 562B xsimkernel.log 330B simulate.log 50B xsimcrash.log 0B xvlog.log 0B compile.log 0B oct28_clk_example.lpr 343B xsim.mem 4KB xsim_0.win64.obj 18KB xsim_1.win64.obj 3KB vivado.pb 43KB write_bitstream.pb 18KB route_design.pb 11KB place_design.pb 11KB opt_design.pb 8KB init_design.pb 4KB xelab.pb 958B clk_display_power_summary_routed.pb 722B clk_display_utilization_synth.pb 242B clk_display_utilization_placed.pb 242B vivado.pb 149B clk_display_methodology_drc_routed.pb 52B clk_display_route_status.pb 44B clk_display_drc_opted.pb 37B clk_display_drc_routed.pb 37B xvlog.pb 16B clk_display_vlog.prj 381B xsim.reloc 2KB xil_defaultlib.rlx 855B xsim.rlx 842B clk_display_io_placed.rpt 97KB clk_display_methodology_drc_routed.rpt 19KB clk_display_clock_utilization_routed.rpt 17KB clk_display_drc_routed.rpt 11KB clk_display_control_sets_placed.rpt 11KB clk_display_utilization_placed.rpt 9KB clk_display_timing_summary_routed.rpt 8KB clk_display_power_routed.rpt 8KB clk_display_utilization_synth.rpt 7KB clk_display_drc_opted.rpt 2KB clk_display_route_status.rpt 588B clk_display_power_routed.rpx 88KB clk_display_methodology_drc_routed.rpx 30KB clk_display_drc_routed.rpx 19KB clk_display_timing_summary_routed.rpx 17KB clk_display_drc_opted.rpx 2KB .vivado.begin.rst 170B .write_bitstream.begin.rst 170B .route_design.begin.rst 170B .place_design.begin.rst 170B .init_design.begin.rst 170B .opt_design.begin.rst 170B .vivado.begin.rst 169B .place_design.end.rst 0B .opt_design.end.rst 0B .write_bitstream.end.rst 0B .init_design.end.rst 0B .Vivado_Synthesis.queue.rst 0B .Vivado_Implementation.queue.rst 0B .vivado.end.rst 0B .vivado.end.rst 0B .route_design.end.rst 0B xsim.rtti 190B clk_display.sdb 5KB clk_dis1_count.sdb 4KB glbl.sdb 4KB clk_div.sdb 2KB ISEWrap.sh 2KB ISEWrap.sh 2KB共 182 条
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