iii
Preface
Read This First
About This Manual
This
Design for Testability Reference Guide
provides information on
developing test strategies for ASIC designs.
The following list summarizes the chapters of this ASIC document.
How to Use This Manual
The chapter highlights are presented in the following text.
Chapter 1 Introduction to Design for Testability
Introduces the subjects of designing for testability in the beginning of the
design process, fault simulation, and dc parametric testing
Chapter 2 Reasons for Using Design for Testability
Discusses the time and money savings achieved by using and integrating
design for testability (DFT) early in your design process. Discusses fault
grading and fault coverage.
Chapter 3 Developing a Testability Strategy
Presents strategies for developing testability techniques
Chapter 4 Test Pattern Requirements
Presents the required and optional TDL pattern types
Chapter 5 Ad Hoc Testability Practices
Recommends some work-arounds and techniques that are useful for
improving your testability
iv
Design for Testability
How to Use This Manual
Chapter 6 Structured Testability Practices
Discusses the different types of scan design testing
Chapter 7 IEEE Standard 1149.1-1990
Provides an overview of the IEEE Std 1149.1 and gives an overview of the
boundary-scan architecture
Chapter 8 Generic Test Access Port
Discusses the generic test access port (GTAP), which is used to enable and
disable various DFT features
Chapter 9 Parallel Module Test
Presents information on parallel module test (PMT), how to use PMT with
MegaModules,such as howto test busesand hook up test busesto devicepins
Chapter 10 Parametric Measurements
Discusses using parametric testing to guarantee conformance to electrical
data sheets and presents information on the use of boundary-scan, pattern
sets, and TDL types
Chapter 11 Automatic Test Pattern Generation
Presents automatic test pattern generation (ATPG) methodologies, such as
path sensitization and full and partial scan
Chapter 12 Test Pattern Generation
Discusses generating test patterns for use by automated test equipment (ATE)
Chapter 13 IEEE Standard 1149.1-Based dc Parametric Testing
Discusses what is required in performing IEEE Standard 1149.1-based dc
parametric testing
Chapter 14 Military ASIC
Summarizes military ASIC documents and the location of military-specific
design information
Appendix A Glossary
Contains important ASIC words, phrases, and software tools
Notational Conventions
v
Notational Conventions
This document uses the following conventions.
❏ Program listings, program examples, and interactive displays are shown
in a special typeface (called courier) similar to a typewriter’s.
Examples use a bold version of the special typeface for emphasis;
interactive displays use a bold version of the special typeface to
distinguish commands that you enter from items that the system displays
(such as prompts, command output, error messages, etc.).
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even
Here is an example of a system prompt and a command that you might
enter:
C: csr -a /user/ti/simuboard/utilities
❏ In syntax descriptions, the instruction, command, or directive is in a bold
typeface font and parameters are in an
italic typeface
. Portions of a
syntax that are in bold should be entered as shown; portions of a syntax
that are in
italics
describe the type of information that should be entered.
Here is an example of a directive syntax:
.asect
section name
,
address
.asect is the directive. This directive has two parameters, indicated by
section name
and
address
. When you use .asect, the first parameter
must be an actual section name; the second parameter must be an
address.
❏ Square brackets ( [ and ] ) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
do not enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:
LALK
16-bit constant [, shift]
The LALK instruction has two parameters. The first parameter,
16-bit
constant
, is required. The second parameter,
shift
, is optional. As this
syntax shows, if you use the optional second parameter, you must
precede it with a comma.
vi
Design for Testability
Information About Cautions and Warnings
❏ Braces ( { and } ) indicate a list. The symbol | (read as
or
) separates items
within the list. Here’s an example of a list:
{ * | *+ | *- }
This provides three choices: *, *+, or *-.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
❏ Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this
directive is:
.byte
value
1
[, ... , value
n
]
This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.
Information About Cautions and Warnings
This book may contain cautions and warnings.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
This is an example of a caution statement.
A caution statement describes asituation that could potentially dam-
age your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
Related Documentation From Texas Instruments
vii
Related Documentation From Texas Instruments
The following list describes related documents of interest to the
Submicron
ASIC Products Design for Testability Reference Guide
(DFT) and includes
corresponding literature numbers.
The ASIC TDL 91 Reference, which discusses ASIC TDL 91 version 5.0. The
TI
Web-based ASIC TDL 91 Reference
provides details about a partic-
ular tool’s capabilities. For more information on the Web, contact your TI
Customer Design Center representative.
The ASIC TDL 91 and Scan Designs Reference, which provides informative
application examples on ASIC TDL 91 and scan designs. Refer to the TI
web-based
ASIC TDL 91 and Scan Designs Reference
.
The Submicron ASIC Products Design for Testability Application Re-
ports, which provide information on designing witha generic test access
port (GTAP) (refer to the Web-based
Generic Test Access Port Applica-
tion Report
), on the RAM Built-In Self-Test (refer to the Web-based
RAM
Built-In Self-Test (BIST) Application Report
), and on the multiplexed par-
allel module test (refer to the Web-based
Multiplexed Parallel Module
Test Application Report
).
The Submicron ASIC Products Design Software Manual (DSM): TIDSS
Design Flow, which describes the Texas Instruments (TI
) Design Sup-
port Software (TIDSS), Release 5 series design flow. The
Web-based
TIDSS Tools Reference
gives details about the specific capabilities and
features of each TIDSS tool.
The Web-based TIDSS Tools Reference, which covers the TIDSS tools in
depth and supports releases in the TIDSS series. This manual (
TIDSS
Design Flow
) will often refer you to the TI
Web-based TIDSS Tools
Reference
for details about a particular tool’s capabilities. For more
information on the Web, contact your TI Customer Design Center
representative.
The Cadence Design Planner User’s Guide, which explains how to use
the Cadence Design Planner floorplanner in the TI Flow.
The Submicron ASIC Products Test Synthesis User’s Guide (literature
number SRGU002B), which describes the Synopsys Test Compiler,
a test tool combining design-for-testability synthesis with automatic test
pattern generation.
The TGC6000/TEC6000 Web-based Design Rules describes design rules
in the flow and provide up-to-date information enabling effective use of
tool-specific design rules and the resolution of errors and warnings
encountered during the design process.
