SPWM.zip_Motor PWM_pwm_pwm sine_sine pwm

// // Lab5A : TMS320F2812 Teaching CD ROM // (C) Frank Bormann // //########################################################################### // // FILE: Lab5A.c // // TITLE: DSP28 T1PWM - output to generate a sine wave , // GP Timer 1 Compare Interrupt every 20 �s // Watchdog active , served in ISR and main-loop // //########################################################################### // // Ver | dd mmm yyyy | Who | Description of changes // =====|=============|======|=============================================== // 2.0 | 11 Nov 2003 | F.B. | adapted to header-files Version 1.00 //########################################################################### #include "DSP281x_Device.h" #include "IQmathLib.h" #pragma DATA_SECTION(sine_table,"IQmathTables"); _iq30 sine_table[512]; // Prototype statements for functions found within this file. void Gpio_select(void); void SpeedUpRevA(void); void InitSystem(void); interrupt void T1_Compare_isr(void); // Prototype for GP Timer1 Compare ISR void main(void) { InitSystem(); // Initialize the DSP's core Registers // Speed_up the silicon A Revision. // No need to call this function for Rev. C later silicon versions SpeedUpRevA(); Gpio_select(); // Setup the GPIO Multiplex Registers InitPieCtrl(); // Function Call to init PIE-unit ( code : DSP281x_PieCtrl.c) InitPieVectTable(); // Function call to init PIE vector table ( code : DSP281x_PieVect.c ) // re-map PIE - entry for GP Timer 1 Compare Interrupt EALLOW; // This is needed to write to EALLOW protected registers PieVectTable.T1CINT = &T1_Compare_isr; EDIS; // This is needed to disable write to EALLOW protected registers // Enable T1 Compare interrupt: PIE-Group2 , interrupt 5 PieCtrlRegs.PIEIER2.bit.INTx5=1; // Enable CPU INT2 which is connected to GP -Timer1 Compare: IER = 2; // Enable global Interrupts and higher priority real-time debug events: EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM // Configure EVA // Assumes EVA Clock is already enabled in InitSysCtrl(); // Drive T1PWM / T2PWM by T1/T2 - logic EvaRegs.GPTCONA.bit.TCMPOE = 1; // Polarity of GP Timer 1 Compare = Active low EvaRegs.GPTCONA.bit.T1PIN = 1; EvaRegs.T1CON.bit.FREE = 0; // Stop on emulation suspend EvaRegs.T1CON.bit.SOFT = 0; // Stop on emulation suspend EvaRegs.T1CON.bit.TMODE = 2; // Continuous up count mode EvaRegs.T1CON.bit.TPS = 0; // prescaler = 1 : 75 MHz EvaRegs.T1CON.bit.TENABLE = 0; // disable GP Timer 1 now EvaRegs.T1CON.bit.TCLKS10 = 0; // internal clock EvaRegs.T1CON.bit.TCLD10 = 0; // Compare Reload when zero EvaRegs.T1CON.bit.TECMPR = 1; // Enable Compare operation EvaRegs.T1PR = 1500; EvaRegs.T1CMPR = EvaRegs.T1PR/2; EvaRegs.EVAIMRA.bit.T1CINT = 1; EvaRegs.T1CON.bit.TENABLE = 1; // enable GP Timer 1 now while(1) { EALLOW; SysCtrlRegs.WDKEY = 0xAA; // and serve watchdog #2 EDIS; } } void Gpio_select(void) { EALLOW; GpioMuxRegs.GPAMUX.all = 0x0; // all GPIO port Pin's to I/O GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6 = 1; // T1PWM active GpioMuxRegs.GPBMUX.all = 0x0; GpioMuxRegs.GPDMUX.all = 0x0; GpioMuxRegs.GPFMUX.all = 0x0; GpioMuxRegs.GPEMUX.all = 0x0; GpioMuxRegs.GPGMUX.all = 0x0; GpioMuxRegs.GPADIR.all = 0x0; // GPIO PORT as input GpioMuxRegs.GPBDIR.all = 0x00FF; // GPIO Port B15-B8 input , B7-B0 output GpioMuxRegs.GPDDIR.all = 0x0; // GPIO PORT as input GpioMuxRegs.GPEDIR.all = 0x0; // GPIO PORT as input GpioMuxRegs.GPFDIR.all = 0x0; // GPIO PORT as input GpioMuxRegs.GPGDIR.all = 0x0; // GPIO PORT as input GpioMuxRegs.GPAQUAL.all = 0x0; // Set GPIO input qualifier values to zero GpioMuxRegs.GPBQUAL.all = 0x0; GpioMuxRegs.GPDQUAL.all = 0x0; GpioMuxRegs.GPEQUAL.all = 0x0; EDIS; } void SpeedUpRevA(void) { // On TMX samples, to get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 internal // control registers bit have to be enabled. The bits are in Device emulation registers. EALLOW; DevEmuRegs.M0RAMDFT = 0x0300; DevEmuRegs.M1RAMDFT = 0x0300; DevEmuRegs.L0RAMDFT = 0x0300; DevEmuRegs.L1RAMDFT = 0x0300; DevEmuRegs.H0RAMDFT = 0x0300; EDIS; } void InitSystem(void) { EALLOW; SysCtrlRegs.WDCR= 0x00AF; // Setup the watchdog // 0x00E8 to disable the Watchdog , Prescaler = 1 // 0x00AF to NOT disable the Watchdog, Prescaler = 64 SysCtrlRegs.SCSR = 0; // Watchdog generates a RESET SysCtrlRegs.PLLCR.bit.DIV = 10; // Setup the Clock PLL to multiply by 5 SysCtrlRegs.HISPCP.all = 0x1; // Setup Highspeed Clock Prescaler to divide by 2 SysCtrlRegs.LOSPCP.all = 0x2; // Setup Lowspeed CLock Prescaler to divide by 4 // Peripheral clock enables set for the selected peripherals. SysCtrlRegs.PCLKCR.bit.EVAENCLK=1; SysCtrlRegs.PCLKCR.bit.EVBENCLK=0; SysCtrlRegs.PCLKCR.bit.SCIAENCLK=0; SysCtrlRegs.PCLKCR.bit.SCIBENCLK=0; SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0; SysCtrlRegs.PCLKCR.bit.SPIENCLK=0; SysCtrlRegs.PCLKCR.bit.ECANENCLK=0; SysCtrlRegs.PCLKCR.bit.ADCENCLK=0; EDIS; } interrupt void T1_Compare_isr(void) { static int index=0; // Serve the watchdog every Timer 0 interrupt EALLOW; SysCtrlRegs.WDKEY = 0x55; // Serve watchdog #1 EDIS; EvaRegs.T1CMPR = EvaRegs.T1PR - _IQsat(_IQ30mpy(sine_table[index]+_IQ30(0.9999),EvaRegs.T1PR/2),EvaRegs.T1PR,0); index +=4; // use every 4th element out of lookup table if (index >511) index = 0; // Reset T1 Compare Interrupt Flag EvaRegs.EVAIFRA.bit.T1CINT = 1; // Acknowledge this interrupt to receive more interrupts from group 2 PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; } //=========================================================================== // End of SourceCode. //===========================================================================