S32K1xx Series Reference Manual
Supports S32K116, S32K118, S32K142, S32K144, S32K146, and
S32K148
Document Number: S32K1XXRM
Rev. 4, 06/2017
Preliminary
S32K1xx Series Reference Manual, Rev. 4, 06/2017
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Preliminary
NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 47
1.2 Organization..................................................................................................................................................................47
1.3 Module descriptions......................................................................................................................................................47
1.3.1 Example: chip-specific information that clarifies content in the same chapter............................................. 48
1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 49
1.4 Register descriptions.....................................................................................................................................................50
1.5 Conventions.................................................................................................................................................................. 51
1.5.1 Notes, Cautions, and Warnings......................................................................................................................51
1.5.2 Numbering systems........................................................................................................................................51
1.5.3 Typographic notation..................................................................................................................................... 52
1.5.4 Special terms..................................................................................................................................................52
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................55
2.2 S32K1xx Series introduction........................................................................................................................................55
2.2.1 S32K14x.........................................................................................................................................................55
2.2.2 S32K11x ........................................................................................................................................................56
2.3 Feature summary...........................................................................................................................................................57
2.4 Block diagram...............................................................................................................................................................60
2.5 Feature comparison.......................................................................................................................................................62
2.6 Applications..................................................................................................................................................................63
2.7 Module functional categories........................................................................................................................................64
2.7.1 ARM Cortex-M4F Core Modules..................................................................................................................66
2.7.2 ARM Cortex-M0+ Core Modules..................................................................................................................66
2.7.3 System modules............................................................................................................................................. 67
2.7.4 Memories and memory interfaces..................................................................................................................68
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Section number Title Page
2.7.5 Power Management........................................................................................................................................68
2.7.6 Clocking.........................................................................................................................................................69
2.7.7 Analog modules............................................................................................................................................. 69
2.7.8 Timer modules............................................................................................................................................... 70
2.7.9 Communication interfaces............................................................................................................................. 70
2.7.10 Debug modules.............................................................................................................................................. 71
Chapter 3
Memory Map
3.1 Introduction...................................................................................................................................................................73
3.2 SRAM memory map.....................................................................................................................................................73
3.2.1 S32K14x: SRAM memory map ....................................................................................................................73
3.2.2 S32K11x: SRAM memory map ....................................................................................................................73
3.3 Flash memory map........................................................................................................................................................74
3.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................74
3.4.1 Read-after-write sequence and required serialization of memory operations................................................75
3.5 Private Peripheral Bus (PPB) memory map..................................................................................................................76
3.6 Aliased bit-band regions for CM4 core........................................................................................................................ 77
Chapter 4
Signal Multiplexing and Pin Assignment
4.1 Introduction...................................................................................................................................................................79
4.2 Functional description...................................................................................................................................................79
4.3 Pad description..............................................................................................................................................................80
4.4 Default pad state........................................................................................................................................................... 81
4.5 Signal Multiplexing sheet............................................................................................................................................. 82
4.5.1 IO Signal Table ............................................................................................................................................. 82
4.5.2 Input muxing table......................................................................................................................................... 83
4.6 Pinout diagrams............................................................................................................................................................ 84
Chapter 5
Security Overview
5.1 Introduction...................................................................................................................................................................85
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5.2 Device security..............................................................................................................................................................85
5.2.1 Flash memory security...................................................................................................................................85
5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................86
5.2.3 Device Boot modes........................................................................................................................................ 87
5.3 Security use case examples...........................................................................................................................................87
5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 87
5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 88
5.3.3 Secure communication...................................................................................................................................89
5.3.4 Component protection....................................................................................................................................90
5.3.5 Message-authentication example................................................................................................................... 91
5.4 Steps required before failure analysis...........................................................................................................................92
5.5 Security programming flow example (Secure Boot).................................................................................................... 93
Chapter 6
Safety Overview
6.1 Introduction...................................................................................................................................................................95
6.2 S32K1xx safety concept............................................................................................................................................... 96
6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST).......................................................................................97
6.2.2 ECC on RAM and flash memory...................................................................................................................98
6.2.3 Power supply monitoring...............................................................................................................................98
6.2.4 Clock monitoring........................................................................................................................................... 99
6.2.5 Temporal protection.......................................................................................................................................99
6.2.6 Operational interference protection............................................................................................................... 99
6.2.7 CRC................................................................................................................................................................101
6.2.8 Diversity of system resources........................................................................................................................ 101
Chapter 7
Core Overview
7.1 ARM Cortex-M4F core configuration..........................................................................................................................103
7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 104
7.1.2 System Tick Timer.........................................................................................................................................104
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