/**
******************************************************************************
* @file system_stm32f10x.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* factors, AHB/APBx prescalers and Flash settings).
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f10x_xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
* the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
* When HSE is used as system clock source, directly or through PLL, and you
* are using different crystal you have to adapt the HSE value to your own
* configuration.
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/** @addtogroup STM32F10x_System_Private_Includes
* @{
*/
#include "stm32f10x.h"
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Defines
* @{
*/
/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
frequency (after reset the HSI is used as SYSCLK source)
IMPORTANT NOTE:
==============
1. After each device reset the HSI is used as System clock source.
2. Please make sure that the selected System clock doesn't exceed your device's
maximum frequency.
3. If none of the define below is enabled, the HSI is used as System clock
source.
4. The System clock configuration functions provided within this file assume that:
- For Low, Medium and High density Value line devices an external 8MHz
crystal is used to drive the System clock.
- For Low, Medium and High density devices an external 8MHz crystal is
used to drive the System clock.
- For Connectivity line devices an external 25MHz crystal is used to drive
the System clock.
If you are using different crystal you have to adapt those functions accordingly.
*/
#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
/* #define SYSCLK_FREQ_HSE HSE_VALUE */
#define SYSCLK_FREQ_24MHz 24000000
#else
/* #define SYSCLK_FREQ_HSE HSE_VALUE */
/* #define SYSCLK_FREQ_24MHz 24000000 */
/* #define SYSCLK_FREQ_36MHz 36000000 */
/* #define SYSCLK_FREQ_48MHz 48000000 */
/* #define SYSCLK_FREQ_56MHz 56000000 */
#define SYSCLK_FREQ_72MHz 72000000
#endif
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
/* #define DATA_IN_ExtSRAM */
#endif
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Variables
* @{
*/
/*******************************************************************************
* Clock Definitions
*******************************************************************************/
#ifdef SYSCLK_FREQ_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_24MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_36MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_56MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_72MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
#else /*!< HSI Selected as System Clock source */
uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
#endif
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef SYSCLK_FREQ_HSE
static void SetSysClockToHSE(void);
#elif defined SYSCLK_FREQ_24MHz
static void SetSysClockTo24(void);
#elif defined SYSCLK_FREQ_36MHz
static void SetSysClockTo36(void);
#elif defined SYSCLK_FREQ_48MHz
static void SetSysClockTo48(void);
#elif defined SYSCLK_FREQ_56MHz
static void SetSysClockTo56(void);
#elif defined SYSCLK_FREQ_72MHz
static void SetSysClockTo72(void);
#endif
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit *
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测速最终.rar_F1测速_c8t6 测速 显示_dinnerdm6_stm32f103c8 速度_stm32捕获速度
共122个文件
o:31个
d:31个
crf:30个
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测速最终.rar_F1测速_c8t6 测速 显示_dinnerdm6_stm32f103c8 速度_stm32捕获速度 (122个子文件)
ssd.uvguix.Administrator 72KB
ssd.axf 341KB
system_stm32f10x.c 36KB
usart.c 5KB
timer.c 3KB
pwm.c 1KB
main.c 1001B
sys.c 876B
key.c 556B
stm32f10x_tim.crf 374KB
stm32f10x_can.crf 361KB
stm32f10x_adc.crf 360KB
stm32f10x_rcc.crf 360KB
stm32f10x_flash.crf 359KB
stm32f10x_i2c.crf 358KB
stm32f10x_usart.crf 358KB
usart.crf 358KB
stm32f10x_fsmc.crf 358KB
main.crf 358KB
stm32f10x_sdio.crf 357KB
stm32f10x_spi.crf 357KB
stm32f10x_gpio.crf 356KB
stm32f10x_dma.crf 356KB
stm32f10x_dac.crf 354KB
stm32f10x_cec.crf 354KB
timer.crf 354KB
system_stm32f10x.crf 354KB
stm32f10x_bkp.crf 354KB
stm32f10x_rtc.crf 353KB
stm32f10x_pwr.crf 353KB
stm32f10x_exti.crf 353KB
sys.crf 353KB
stm32f10x_wwdg.crf 353KB
misc.crf 353KB
stm32f10x_iwdg.crf 352KB
pwm.crf 352KB
stm32f10x_crc.crf 352KB
stm32f10x_dbgmcu.crf 352KB
key.crf 352KB
stm32f10x_dbgmcu.d 4KB
stm32f10x_flash.d 4KB
stm32f10x_usart.d 4KB
stm32f10x_fsmc.d 4KB
stm32f10x_gpio.d 4KB
stm32f10x_exti.d 4KB
stm32f10x_wwdg.d 4KB
stm32f10x_sdio.d 4KB
stm32f10x_iwdg.d 4KB
stm32f10x_spi.d 4KB
stm32f10x_rcc.d 4KB
stm32f10x_dma.d 4KB
stm32f10x_crc.d 4KB
stm32f10x_i2c.d 4KB
stm32f10x_rtc.d 4KB
stm32f10x_can.d 4KB
stm32f10x_cec.d 4KB
stm32f10x_adc.d 4KB
stm32f10x_tim.d 4KB
stm32f10x_dac.d 4KB
stm32f10x_bkp.d 4KB
stm32f10x_pwr.d 4KB
system_stm32f10x.d 4KB
misc.d 3KB
usart.d 3KB
main.d 3KB
timer.d 3KB
pwm.d 3KB
sys.d 3KB
key.d 3KB
startup_stm32f10x_md.d 81B
Target_1_STM32F103C8_1.0.0.dbgconf 7KB
ssd_Target 1.dep 114KB
RTE_Device.h 63KB
stm32f10x_conf.h 4KB
sys.h 3KB
usart.h 1KB
RTE_Components.h 1KB
timer.h 106B
key.h 94B
pwm.h 82B
ssd.hex 12KB
ssd.htm 48KB
Packs_Target 1.htm 44KB
ssd.build_log.htm 9KB
ssd.lnp 1KB
startup_stm32f10x_md.lst 44KB
ssd.map 126KB
stm32f10x_tim.o 523KB
stm32f10x_adc.o 443KB
stm32f10x_i2c.o 437KB
stm32f10x_rcc.o 435KB
stm32f10x_usart.o 431KB
stm32f10x_flash.o 431KB
stm32f10x_sdio.o 430KB
stm32f10x_can.o 427KB
stm32f10x_spi.o 422KB
stm32f10x_fsmc.o 416KB
stm32f10x_gpio.o 415KB
stm32f10x_cec.o 407KB
stm32f10x_rtc.o 407KB
共 122 条
- 1
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