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learn-the-architecture系列
· 作者:代码改变世界ctw
前言
推荐序
致谢
1. ARM 架构的介绍
1.1、Overview
1.2、About the Arm architecture
1.3、架构(architecture)到底是什么意思呢
1.4、Architecture and micro-architecture
1.5、Arm architecture的版本
1.6、Arm documentation的定义
1.7、ARM timeline
2. ARM指令集介绍
2. 1、Overview
2. 2、为什么要关心ISA
2. 3、Instruction sets in the Armv8-A
2. 4、 Instruction set resources
2. 5、Simple sequential execution
2. 6、Registers in AArch64
2. 6.1 、General-purpose registers
2. 6.2、 特殊寄存器
2. 6.3、 System registers
2. 7 、 Data processing
2. 7.1 、Arithmetic and logic operations
2. 7.2 、 Floating point
2. 7.2.1 、Is floating point support optional?
2. 7.3 、 Bit manipulation
2. 7.4 、 Extension and saturation
2. 7.4.1 、Sub-register-sized integer data processing
2. 7.5 、 Format conversion
2. 7.6 、 Vector data
2. 8 、 Loads and stores
2. 8.1、Load-Store Single Register 单寄存器读写
2. 8.2、Load-Store Single Register (unscaled offset) offset为-256 ~ +256对齐读写
2. 8.3、Load-Store Pair 双寄存器读写
2. 8.4、Load-Store Non-temporal Pair 直接读写外存,跳过cache
2. 8.5、Load-Store Unprivileged 以EL0身份读写
2. 8.6、Load-Store Exclusive 独占
2. 8.7、Load-Acquire / Store-Release 带有aruire/release语义的读写
2. 8.8、总结以上指令
2. 9 、 Program flow
2. 9.1、条件跳转指令
2. 9.2、无条件跳转label指令
2. 9.3、无条件跳转register指令
2. 10 、 Function calls
2. 11 、 Procedure Call Standard
2. 12 、 System calls
2. 13、学习资料
3. AMBA_AXI的介绍
术语
3.1、简介
3.2、AMBA是什么? 为什么要用AMBA?
3.2.1 哪些地方使用AMBA?
3.2.2 AMBA的有点?
3.2.3 AMBA的发展历史
3.2.3.1 AMBA 1
3.2.3.2 AMBA 2
3.2.3.3 AMBA 3
3.2.3.4 AMBA 4
3.2.3.5 AMBA 5
3.3 AXI protocol overview
3.3.1 AXI in a multi-master system
3.3.2 AXI channels
3.3.3 Main AXI features
3.4 Channel transfers and transactions
3.4.1 通道握手 :Channel handshake
3.4.2 Differences between transfers and transactions
3.4.3 Channel transfer examples
3.4.4 Write transaction: single data item
3.4.5 Write transaction: multiple data items
3.4.6 Read transaction: single data item
3.4.7 Read transaction: multiple data items
3.4.8 Active transactions
3.5 Channel signals
3.5.1 Write channel signals
3.5.2 Read channel signals
3.5.3 Data size, length, and burst type
3.5.4 Protection level support
3.5.5 Cache support
3.5.6 Response signaling
3.5.7 Write data strobes
3.5.8 Atomic accesses with the lock signal
3.5.9 Quality of service
3.5.10 Region signaling
3.5.11 User signals
3.5.12 AXI channel dependencies
3.6 Atomic accesses
3.6.1 Locked accesses
3.6.2 Exclusive accesses
3.6.3 Exclusive access hardware monitor operation
3.6.4 Exclusive transaction pairs: both pass
3.6.5 Exclusive transaction pairs: one pass, one fail
3.7 Transfer behavior and transaction ordering
3.7.1 Examples of simple transactions
3.7.2 Transfer IDs
3.7.3 Write transaction ordering rules
3.7.4 Read transaction ordering rules
3.7.5 Read and write channel ordering
3.7.6 Unaligned transfer start address
3.7.7 Endianness support
3.7.8 Read and write interface attributes
4. Trustzone的介绍
4.1、简介
4.2、TrustZone是什么?
4.3、processor中的Trustzone技术
4.3.1. 两个安全状态: secure、non-secure
4.3.2. 安全状态的切换
4.3.3. 虚拟地址空间
4.3.4. 物理地址空间
4.3.5. cache
4.3.6. TLB : Translation Lookaside Buffer
4.3.7. SMC exceptions
4.3.8. 安全虚拟化
4.4、系统架构中的Trustzone技术
4.4.1. Slave devices: peripherals, and memories
4.4.3 Enforcing isolation
4.4.4 Bus masters
4.4.5 M and R profile Arm processors
4.4.6 Interrupts
4.4.7 Handling interrupts
4.4.8 Debug, trace, and profiling
4.4.9 Other devices
5. 异常模型介绍
5.1 Overview
5.2 Privilege and Exception levels
5.2.1. Types of privilege
5.2.2. Memory privilege
5.2.3. Register access
5.3 Execution and Security states
5.3.1. Execution states
5.3.2. Security state
5.3.3. Changing Execution state
5.3.4. Changing Security state
5.3.5. Implemented Exception levels and Execution states
5.4 Exception types
5.4.1. Synchronous exceptions
5.4.2. Asynchronous exceptions
5.4.3. IRQ and FIQ
5.4.4. SError
5.5 Handling exceptions
5.5.1. Exception terminology
5.5.2. Taking an exception
5.5.3. Routing asynchronous exceptions
5.5.4. Determining which Execution state an exception is taken to
5.5.5. Returning from an exception
5.5.6. Exception stacks
5.6 The vector tables
6. GICV3/4的介绍
6. 1 Overview
6. 2 Before you begin
6. 3 What is a Generic Interrupt Controller?
6. 3.1. A brief history of the Arm CoreLink GIC
6. 4 Arm CoreLink GIC fundamentals
6. 4.1. Interrupt types
6. 4.1.1 How interrupts are signaled to the interrupt controller
6. 4.2. Interrupt state machine
6. 4.2.1 Level sensitive interrupts
6. 4.2.2 Edge-triggered interrupts
6. 4.3. Target interrupts
6. 4.4. Security model
6. 4.4.1 Impact on software
6. 4.4.2 Support for single Security state
6. 4.5. Programmer’s model
6. 4.5.1 Distributor (GICD_*)
6. 4.5.2 Redistributors (GICR_*)
6. 4.5.3 CPU interfaces (ICC*ELn)
6. 5 Configuring the Arm CoreLink GIC
6. 5.1. Global settings
6. 5.2. Settings for each PE
6. 5.2.1 Redistributor configuration
6. 5.2.2 CPU interface configuration
6. 5.2.3 PE configuration
6. 5.2.4 SPI, PPI and SGI configuration
6. 5.2.5 Arm CoreLink GICv3.1 and the extended INTID ranges
6. 5.2.6 Setting the target PE for SPIs
6. 6 Handling interrupts
6. 6.1. Routing a pending interrupt to a PE
6. 6.2. Taking an interrupt
6. 6.2.1 Example of interrupt handling
6. 6.3. Running priority and preemption
6. 6.4. End of interrupt
6. 6.5. Checking the current state of the system
6. 6.5.1 Highest priority pending interrupt and running priority
6. 6.5.2 State of individual INTIDs
6. 7 Sending and receiving Software Generated Interrupts
6. 7.1. Generating SGIs
6. 7.1.1 Controlling the SGI ID
6. 7.1.2 Controlling the target
6. 7.1.3 Controlling the Security state and grouping
6. 7.2. Comparison of GICv3 and GICv2
6. 8 Example
6. 9 Appendix: Legacy operation
7. 安全侧虚拟化隔离技术的白皮书
7.1 Introduction
7.2 Background - A brief history of Arm TrustZone
7.3 Today’s challenges in the Secure world
7.3.1. Trusted application ecosystem challenges
7.3.2. Integration of code from multiple vendors in the Secure world
7.3.3. The principle of least privilege
7.3.4. Required solution
7.4 Virtualization in Secure world
7.5 Secure partitions
7.6 Migration of the secure ecosystem to Secure EL2
7.6.1. Impacts on trusted operating systems
7.6.2. Impacts on Normal world software
7.7 Conclusion
7.8 Glossary
8. 内存管理简介
8.1 Overview
8.2 What is memory management?
8.2.1. Why is memory management needed?
8.3 Virtual and physical addresses
8.4 The Memory Management Unit (MMU)
8.4.1. Table entry
8.4.2. Multilevel translation
8.5 Address spaces in Armv8-A
8.5.1. Address sizes
8.5.1.1 Size of virtual addresses
8.5.1.2 Size of physical addresses
8.5.1.3 Size of intermediate physical addresses
8.5.2. Address Space Identifiers - Tagging translations with the owning process
8.5.3. Virtual Machine Identifiers - Tagging translations with the owning VM
8.5.4. Common not Private
8.6 Controlling address translation
8.6.1. Translation table format
8.7 Translation granule
8.7.1. The starting level of address translation
8.7.2. Registers that control address translation
8.7.3. MMU disabled
8.8 Translation Lookaside Buffer maintenance
8.8.1. Format of a TLB operation
8.9 Address translation instructions
9. 内存管理模型
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- m0_751075262023-07-11感谢大佬分享的资源,对我启发很大,给了我新的灵感。
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