fifo_UVM.zip

=============================================================================== Module : my_if =============================================================================== SCORE LINE TOGGLE FSM 95.83 -- 95.83 -- Source File(s) : /home/fguo/Desktop/fifo/my_if.sv Module self-instances : SCORE LINE TOGGLE FSM NAME 95.83 -- 95.83 -- top_tb.my_if1 ------------------------------------------------------------------------------- Toggle Coverage for Module : my_if Total Covered Percent Totals 10 8 80.00 Total Bits 48 46 95.83 Total Bits 0->1 24 23 95.83 Total Bits 1->0 24 23 95.83 Ports 4 4 100.00 Port Bits 8 8 100.00 Port Bits 0->1 4 4 100.00 Port Bits 1->0 4 4 100.00 Signals 6 4 66.67 Signal Bits 40 38 95.00 Signal Bits 0->1 20 19 95.00 Signal Bits 1->0 20 19 95.00 Port Details Toggle Toggle 1->0 Toggle 0->1 Direction wclk Yes Yes Yes INPUT rclk Yes Yes Yes INPUT wrst_n Yes Yes Yes INPUT rrst_n Yes Yes Yes INPUT Signal Details Toggle Toggle 1->0 Toggle 0->1 winc Yes Yes Yes rinc No No Yes wdata[7:0] Yes Yes Yes wfull Yes Yes Yes rempty No Yes No rdata[7:0] Yes Yes Yes ------------------------------------------------------------------------------- =============================================================================== Module Instance : top_tb.my_if1 =============================================================================== Instance : SCORE LINE TOGGLE FSM 95.83 -- 95.83 -- Instance's subtree : SCORE LINE TOGGLE FSM 95.83 -- 95.83 -- Module : SCORE LINE TOGGLE FSM NAME 95.83 -- 95.83 -- my_if Parent : SCORE LINE TOGGLE FSM NAME 100.00 100.00 100.00 -- top_tb Subtrees : no children ---------------- ------------------------------------------------------------------------------- Since this is the module's only instance, the coverage report is the same as for the module. =============================================================================== Module : rptr_empty =============================================================================== SCORE LINE TOGGLE FSM 97.79 100.00 95.59 -- Source File(s) : /home/fguo/Desktop/fifo/rptr_empty.v Module self-instances : SCORE LINE TOGGLE FSM NAME 97.79 100.00 95.59 -- top_tb.asyn_fifo1.rpte_empty11 ------------------------------------------------------------------------------- Line Coverage for Module : rptr_empty Line No. Total Covered Percent TOTAL 6 6 100.00 ALWAYS 38 3 3 100.00 ALWAYS 52 3 3 100.00 37 always@(posedge rclk or negedge rrst_n) 38 1/1 if(!rrst_n) 39 1/1 {rptr,rbin} <= 0; 40 else 41 1/1 {rptr,rbin} <= {rgnext,rbnext}; 42 43 assign raddr = rbin[ADDRSIZEL-1 : 0]; 44 45 assign rbnext = rbin + (rinc & ~rempty); 46 47 assign rgnext = rbnext>>1 ^ rbnext; 48 49 //assign rempty = (rq2_wptr == rptr) ? 1 : 0; rempty为什么不能写成组合逻辑 50 assign rempty_val = (rgnext == rq2_wptr) ? 1 : 0; 51 always@(posedge rclk or negedge rrst_n) 52 1/1 if(!rrst_n) 53 1/1 rempty <= 1; 54 else 55 1/1 rempty <= rempty_val; ------------------------------------------------------------------------------- Toggle Coverage for Module : rptr_empty Total Covered Percent Totals 11 8 72.73 Total Bits 68 65 95.59 Total Bits 0->1 34 32 94.12 Total Bits 1->0 34 33 97.06 Ports 7 5 71.43 Port Bits 36 34 94.44 Port Bits 0->1 18 17 94.44 Port Bits 1->0 18 17 94.44 Signals 4 3 75.00 Signal Bits 32 31 96.88 Signal Bits 0->1 16 15 93.75 Signal Bits 1->0 16 16 100.00 Port Details Toggle Toggle 1->0 Toggle 0->1 Direction rrst_n Yes Yes Yes INPUT rclk Yes Yes Yes INPUT rinc No No Yes INPUT rq2_wptr[4:0] Yes Yes Yes INPUT raddr[3:0] Yes Yes Yes OUTPUT rptr[4:0] Yes Yes Yes OUTPUT rempty No Yes No OUTPUT Signal Details Toggle Toggle 1->0 Toggle 0->1 rbin[4:0] Yes Yes Yes rbnext[4:0] Yes Yes Yes rgnext[4:0] Yes Yes Yes rempty_val No Yes No ------------------------------------------------------------------------------- =============================================================================== Module Instance : top_tb.asyn_fifo1.rpte_empty11 =============================================================================== Instance : SCORE LINE TOGGLE FSM 97.79 100.00 95.59 -- Instance's subtree : SCORE LINE TOGGLE FSM 97.79 100.00 95.59 -- Module : SCORE LINE TOGGLE FSM NAME 97.79 100.00 95.59 -- rptr_empty Parent : SCORE LINE TOGGLE FSM NAME 98.08 -- 98.08 -- asyn_fifo1 Subtrees : no children ---------------- ------------------------------------------------------------------------------- Since this is the module's only instance, the coverage report is the same as for the module. =============================================================================== Module : asyn_fifo =============================================================================== SCORE LINE TOGGLE FSM 98.08 -- 98.08 -- Source File(s) : /home/fguo/Desktop/fifo/asyn_fifo.v Module self-instances : SCORE LINE TOGGLE FSM NAME 98.08 -- 98.08 -- top_tb.asyn_fifo1 ------------------------------------------------------------------------------- Toggle Coverage for Module : asyn_fifo Total Covered Percent Totals 16 14 87.50 Total Bits 104 102 98.08 Total Bits 0->1 52 51 98.08 Total Bits 1->0 52 51 98.08 Ports 10 8 80.00 Port Bits 48 46 95.83 Port Bits 0->1 24 23 95.83 Port Bits 1->0 24 23 95.83 Signals 6 6 100.00 Signal Bits 56 56 100.00 Signal Bits 0->1 28 28 100.00 Signal Bits 1->0 28 28 100.00 Port Details Toggle Toggle 1->0 Toggle 0->1 Direction wclk Yes Yes Yes INPUT rclk Yes Yes Yes INPUT wrst_n Yes Yes Yes INPUT rrst_n Yes Yes Yes INPUT winc Yes Yes Yes INPUT rinc No No Yes INPUT wdata[7:0] Yes Yes Yes INPUT wfull Yes Yes Yes OUTPUT rempty No Yes No OUTPUT rdata[7:0] Yes Yes Yes OUTPUT Signal Details Toggle Toggle 1->0 Toggle 0->1 waddr[3:0] Yes Yes Yes raddr[3:0] Yes Yes