论文研究-Experimental investigation on silicon microchannel plate electron multiplier.pdf

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硅微通道板电子倍增器的实验研究,王国政,兰春蕾,采用光辅助电化学腐蚀工艺制备出高纵横比的硅微通道阵列。研究了硅的各向异性腐蚀机理、工艺参数、诱导坑阵列和通道形状,讨论了
山国科技论文在线 http://www.paper.edu.cn etching(KOH) The PEC etching of silicon microchannel arrays was performed in hydrofluoric acid in three electrodes electrolyzing cell controlled by a potentiostat of model 2273. a platinum grid was used as counter electrode, silicon wafer as the working electrode, and saturated calomel electrode as the reference, a halogen lamp as the excited light source concentration of hf solution is 3-5wt%o. To remove hydrogen bubbles from sample surface and solution, the electrolyte was stirred slightly 80 The temperature of electrolyte cell was controlled at 300 k by a temperature controller Finally, the silicon microchannel array with though pores was released by thinning from backside of wafer By the process of oxidation and LPCVD, we prepared silicon dioxide thin film dynode with 85 sandwich structure that comprising insulation layer, conductive layer and secondary electron emission(SeE)layer. The insulating layer made by the oxidation process of silicon microchannel arrays and the lPcvd of SiO2 and Si3N4, the conducting layer by LPCVd of polycrystalline silicon or amorphous silicon, and see layer by silicon surface oxidation or atomic layer deposition(alD) 90 The morphology of the surface and the wall of silicon microchannel array were observed and studied by SEM. The electron gain of Si-MCP electron multiplier was tested by Special dynamic Testing System for Photoelectron Multiplier developed based on Ultraviolet-Photoelectron Method Photo electrochemical(PEC) etching researches were focus on Ill-V semiconductors electronic and photonic devices, silicon MEMs devices and silicon three-dimensional micromachining. The anisotropy electrochemical etching of silicon relies upon the reaction of the 100 anodic dissolution of silicon in aqucous fluoride- containing media. the rcaction formula is shown as follow Si+2H.0 +2h- Sio +4H+2 Si+ 6hfaq->h,SiF +H,+2H Because the reaction needs holes, the anodic reaction can take place easily for p-type silicon 105 wafer. The illumination must be applied on silicon to produce holes for n-silicon wafer that a photo-electrochemical process can be keeping. So, whether the silicon wafers is n-type or p-type, the mcchanism of clcctrochcmical rcactions for macroporous silicon arrays arc the samc, namcl he anodic reaction 3 国科技论文在线 http://www.paper.edu.cn 60 已40 20 voltage /v 110 Fig. 2. Typical I-V characteristics curves of n-type silicon wafer in HF solution under enough illumination is the first peak of the curve, called critical current density I-V characteristic curve for enough illuminated n-type silicon in HF solution is shown in Fig. 2. the first peak of the curve, is called critical current density. When etching current 115 density is lower than silicon electrochemistry controlled by anodic reaction, a porous silicon or macroporous silicon structure is formed on the interface of silicon/HF. When etching current density is higher than the silicon electrochemical process is controlled by fluorine ion diffusion in solution, an electrochemical polishing or a current oscillation occur. According to Lehmann theory can be described in formula 120 3/2 exp(- where (3.3x10 mA/cm")is a constant, (0.345eV) activation energy in electrochemical reaction, c(wt%o) concentration of HF solution, t (K) solution temperature, equals 1.38x10-J/K. Electrochemical etching parameters can be determined by measuring in silicon electrochemical system The channel growth in silicon divides the interface of silicon/HF into two areas: (i)the pore ips, where all (or most) of the current is flowing;(ii) the pore walls and the remaining silicon surfacc wherc no current is flowing. the onc of the important factors for the pore-formation is the photo-generated holes focused on the pore-tip by the space-charge-region in PEC process, and the channel wall was effectively passivated against dissolution. So, there was the anisotropy 130 channel growth The microchannel diameter is a function of the etching current density and critical current density that can be described by the cquation 135 where is the length of repeat unit of the pattern. Because the concentration reducing of HF in the channel tip zones and the arcas sidewall incrcasing during the microchannel ctching proccss the diameter will increase, so the etching current density must be modulated accordingly According to theoretical analysis, the relation among the microchannel growth rate (in cm/s) and (in A/cm")can be described by the equation, 140 (5) where (1.602x10C)is elementary charge, (5X10/cm") is atomic density of silicon 4 山国科技论文在线 http://www.paper.edu.cn and n is dissolution valence(number of charge carriers per dissolved silicon atom) In order to study the change of the critical current density the length of microchannel growth in different time period were measured by making mark per hour in the optimum etching 145 process conditions, as shown in Fig 3. By fitting on the curve(squares) of microchannel growth length and calculation from equation (5) and neglecting the leak current from channel wall, we can obtain the curve of variation in etching time, as shown in Fig 3(solid line) 350 300 250 200 150 100 4吕 100205300400500600 ching time(min) Fig. 3. Experiment data of microchannel length(square)versus etching time, and critical current density(solid line) 150 from fitting data and calculating Here we proposed indirectly to determine the variation of in PEC etching process from experimental data, wiich can be considered the steady-diameler growth condition of silicon microchannel. o was taken as a control curve or channel growth curve to control the PEC 155 ctching of silicon microchannel arrays automatically The backside thinning for rclcasc of silicon microchannel structure was carricd out etching and chemical mechanical polishing An oxidation step was firstly performed to protect the microchannel structure from damage in wet releasing process, where the concentration of TMAH 160 is 30 wt%, etching temperature 80 C. when the etched surface met with the channel tips, the wet releasing process stopped, and the layer of silicon oxide was stripped by hf solution, then chemical mechanical polishing for silicon microchannel arrays was conducted Thcre is a limited varicty of cross- scction shapes of silicon microchannel arrays attained b electrochemical etching. According to the work from T. Trifonov 9, the post-shaping and 165 widening of silicon microchannel arrays were performed by repeated oxidation and oxide striping steps, or by anisotropic etching in TMAH solution. Careful choice of concentration(lwt%) alcohol additives (10% IPA)and temperature (5C) of TMAH solution allows for certain crystallographic directions to be preferentially etched. In this way, channel cross-section with squarc and dimension widening can bc attained. Thc morphology of silicon microchannel arrays 170 after post-shaping is shown in Fig 4 山国科技论文在线 http://www.paper.edu.cn 17 Jul-es Fe59085e ky x3aB Fig. 4. Morphology of silicon microchannel arrays after post-shaping process (a) sample photos, (b )end surface of microchannel arrays, 5 um of side length, I um of channel space, (c)profile of microchannel with 7 channel bias 175 angle Silicon microchannel array is a semiconductor substratc that must be trcated into insulation one to meet the demand of the electric properties as an electron multiplier. SiO2 thin film is a typical insulation media with is about 10 -10 Q2 cm of resistivity and that can be made by 180 thermal oxidation or LPCVD compatible to the general semiconductor process SeE laver onducting layer 32 Insulating laver Silicon substrate Fig. 5.(a) Schematic diagram of Dynode structure of Si- MCP, where Sio, (SEE layer)/PolySi(conductive layer, 10-10Q2 cm)/Sio2 +Si, N4 (insulation layer)/ Si-MCP substrate, (b) Photo of 25mm of diameter of Si-MCP 185 with silicon thin film dynode Because of the yield of secondary electron emission(SEE) is nearly close to the glass MCP, the Sio2 thin film can be also selected as see layer of the dynode. There must be a conducti layer, a polycrystalline or amorphous silicon thin film, beneath the SEE layer in order to avoid the 190 charge effect in the course of secondary electron emission. The structure of continuous thin film dynode of Si-MCP was designed to be three layers as below, comprised of insulation, conductive and see layers, shown in Fig.5(a) The insulation layer of SiO2 was first prepared at the temperature of 950-1100C by dry-wel-dry oxidation, then the thickening of insulation layer was performed by LPCVd Sio or 195 Si3N4. The conductive layer of Poly Si was made at the temperature of 540-580C by LPCVD, its resistance can be controlled by oxygen doping. Finally, a low temperature oxidation was carried out to form 5-1Onm of SiO2 surfacc as thc SEE laycr. Fig. 5 (b) is thc photo of silicon microchannel plate electron multiplier from new process 200 After the silicon microchannel array and thin film dynode were prepared, the working electrodes of Ni-Cr alloy were deposited on double sides of silicon microchannel plate. the 山国科技论文在线 http://www.paper.edu.cn samples of silicon microchannel plate for test was 25mm of the plate diameter, 5 um of thc channel side length, I Aun of the channel space, more than 40 aspect ratio, and 7 channel bias angle. The electron gain of Si-MCP is 165 at 680V working voltage that easured by Special Dynamic Testing 5 System for Photoelectron Multiplier developed based on Ultraviolet-Photoelectron Method We obtained the samples of silicon microchannel plate with 25mm of the plate diameter, 4-6 um of channel side size, 2 um of the channel space, more than 40 of aspect ratio, and 7 channel bias angle. The variation of in PEC ctching proccss can be measured indirectly from 210 experimental data, witch can be considered the steady-diameter growth condition of Silicon Microchannel arrays. The insulator was selected SiO2 and Si3 N4, conductive layer Poly-silicon and emission layer Sio2, prepared by oxidation, LPCVD. The electron gain of Si-MCP is 165 at 680v working voltage. The experimental study indicates that the technique of silicon microchannel plate is fcasiblc. Higher working voltage of Si-MCP was not applicd in our 215 experiment because of breakdown voltage limitation, that need to further improve and enhance the dielectric breakdown characteristics for insulation layer of Si-mcp dynode The authors would like to thank Prof. He Xuefeng and wang Shengqiang. Microsystem Research Center of Chongqing University, China, for Lheir help in LPC Vd thin Hilm process 220 1]J.R. Horton, G. W. Tasker, J.J. Fijol [2]J.R. Horton, C. Elizaberth, G. W. Tasker, "Microchannel electron Multiplier "U SA Patent 508624, 1992 [3] Beetz, C.P., Boerstler, R. W, Steinbeck, J. and Winn, D. R, " Silicon etching process for making microchannel plates. USA Patent 5997713, 1999 225 [4]Beetz, C P, Boerstler, R, Steinbeck, J, Lemieux, B and Winn, D.R., Silicon-micromachined microchannel plates. "Nuclear Inst and Methods in Physics Research, A, 442(1-3): 443-451(2000) 15O. H.W. Siegmund, A S. Tremsin, J. V. Vallerga, C. P. Beetz, R. W. Boerstler, J. Yang and D.R. Winn, Progress in the development of silicon microchannel plates, Proc. SPIE, 4497, 139-148(2002 [61O H. W. Siegmund, "High-performance microchannel plate detectors for UV/visible astronomy, Nuclear Inst 230 and Methods in Physics Research, A, 525(1-2),12-16(2004) [7 M. Gertsenshteyn, Silicon Microchannel Plate Large Area UV Detector, NASA SBIR, 07-IS1 05-9739 2007 [8V. Lehmann, [Electrochemistry of silicon], Wiley-VCH Weinheim publisher, Germany, 2002 [9]T. Trifonov, M. Garin, A. Rodriguez, P. Ortega, L. F. Marsal and R. Alcubilla, " Post-etching shaping of 235 macroporous silicon, "Proc. SPIE, 6593, 65931Q(2007) [10 Tian Jingquan, Zhang Baifu, et aL, UV-photo-method for measurement of MCP characteristic parameters, Proc.SPE,1230.228-230(1990) 硅微通道板电子倍增器的实验研究 240 王国政,兰春蕾,王洋,程宏昌,秦旭磊,姜振华,端木庆铎 长春理工大学理学院,长春130022) 摘要:采用光辅助电化学腐蚀工艺制备出高纵横比的硅微诓道阵列。研究了硅的冬向异性腐 蚀机理、工艺参数、诱导坑阵列和通道形状,讨论了微通道稳定生长时的腐蚀电流密度。之 后,通过 LPCVD工艺制作了SO2薄膜打拿极。研究和制作了打拿极的绝缘、寻电和电子 245发射层。得到了板面直径25mm、通道尺寸4-6um、通道间隔1-2μm、长径比高于40、通道 倾斜角为7°硅通微通道板样品,在680√工作电压下样品的电子培益为165。通过对硅徼通 道板的实验研究说明了硅微通道板工艺是可行的。 关键词:硅;微通道板;电化学刻蚀;打拿极;电子倍增器;夜视 中图分类号:TN144

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