Features
3
December 2004 − Revised September 2006 SGUS053B
1 Features
D High-Performance Static CMOS Technology
− 150 MHz (6.67-ns Cycle Time)
− Low-Power (1.8-V Core at 135 MHz, 1.9-V
Core at 150 MHz, 3.3-V I/O) Design
− 3.3-V Flash Voltage
D JTAG Boundary Scan Support
†
D High-Performance 32-Bit CPU
(TMS320C28x)
− 16 x 16 and 32 x 32 MAC Operations
− 16 x 16 Dual MAC
− Harvard Bus Architecture
− Atomic Operations
− Fast Interrupt Response and Processing
− Unified Memory Programming Model
− 4M Linear Program Address Reach
− 4M Linear Data Address Reach
− Code-Efficient (in C/C++ and Assembly)
− TMS320F24x/LF240x Processor Source
Code Compatible
D On-Chip Memory
− Flash Devices: Up to 128K x 16 Flash
(Four 8K x 16 and Six 16K x 16 Sectors)
− ROM Devices: Up to 128K x 16 ROM
− 1K x 16 OTP ROM
− L0 and L1: 2 Blocks of 4K x 16 Each
Single-Access RAM (SARAM)
− H0: 1 Block of 8K x 16 SARAM
− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
D Boot ROM (4K x 16)
− With Software Boot Modes
− Standard Math Tables
D External Interface
− Up to 1M Total Memory
− Programmable Wait States
− Programmable Read/Write Strobe Timing
− Three Individual Chip Selects
D Clock and System Control
− Dynamic PLL Ratio Changes Supported
− On-Chip Oscillator
− Watchdog Timer Module
D Three External Interrupts
D Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
D 128-Bit Security Key/Lock
− Protects Flash/ROM/OTP and L0/L1
SARAM
− Prevents Firmware Reverse Engineering
D Three 32-Bit CPU-Timers
D Motor Control Peripherals
− Two Event Managers (EVA, EVB)
− Compatible to 240xA Devices
D Serial Port Peripherals
− Serial Peripheral Interface (SPI)
− Two Serial Communications Interfaces
(SCIs), Standard UART
− Enhanced Controller Area Network
(eCAN)
− Multichannel Buffered Serial Port
(McBSP) With SPI Mode
D 12-Bit ADC, 16 Channels
− 2 x 8 Channel Input Multiplexer
− Two Sample-and-Hold
− Single/Simultaneous Conversions
− Fast Conversion Rate: 80 ns/12.5 MSPS
D Up to 56 Individually Programmable,
Multiplexed General-Purpose Input/ Output
(GPIO) Pins
D Advanced Emulation Features
− Analysis and Breakpoint Functions
− Real-Time Debug via Hardware
D Development Tools Include
− ANSI C/C++ Compiler/Assembler/Linker
− Supports TMS320C24x™/240x
Instructions
− Code Composer Studio™ IDE
− DSP/BIOS™
− JTAG Scan Controllers
†
[Texas Instruments (TI) or Third-Party]
− Evaluation Modules
− Broad Third-Party Digital Motor Control
Support
D Low-Power Modes and Power Savings
− IDLE, STANDBY, HALT Modes Supported
− Disable Individual Peripheral Clocks
D Package Options
− 172-Pin Ceramic Quad Flatpack (HFG)
D Temperature Options:
− M: −55°C to 125°C (HFG)
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
†
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
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