ZYNQ 7000用户手册

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Date Version Revision 08/08/2012 1.2 Reorganized, clarified, and expanded Chapter 19 to include programming models (Cont'd)(added sections 19.1.3 Notices, 19.3 Programming Guide, and 19.5.1 MIO Programming). Updated Table 22-2 and Table 22-3 in Chapter 22. Added section CPU Clock Divisor Restriction in Chapter 25. Updated Table 26-4 in Chapter 26 Clarified section 27. 3 Iy0 Signals in Chapter 27. Added section 28. 1.2 Notices in Chapter 28 Clarified Mapping Summary and updated Table 29-1, Table 29-3, and Table 29-5 in Chapter 29. Added section 30. 1.3 Notices in Chapter 30. Updated data sheet references n section A.3.1 Zynq-7000 AP SoC Documents of Appendix A Updated register database in sections B 3 Module Summary through B 34 USB Controller(usb) in Appendix B 10/30/2012 1.3 Changed product name from Extensible Processing Platform(EPP)to All Programmable SoC(AP SoC)throughout document Added Table 1-1. Added 2.1.1 Notices, 2.4 PS-PL Voltage Level Shifter Enables, A summary of the dedicated PS signal pins is shown in Table 2-2., VREF Source Considerations, updated Table 2-2, and added warning to 2.5.7 MIO Pin Electrical Parameters. Added Initialization of Ll Caches, 3.2. 4 Memory Ordering, expanded 3.2.5 Memory Management Unit(MMU), added Cache Lockdown by Way Sequence and 3. 9 CPU Initialization Sequence. Added 7z007s and 7z010 Device Notice and expanded Table 4-7. Updated and expanded tables in 6.3. 4 Quad-SPI Boot through 6.3. 13 Post BootROM State, reworked 6.3.6 Debug Status, and added 6.3. 13 Post BootROM State and AXI and dMA Done status Interrupts. Reworked able 7-4. Added 8.1.2 Notices, Interrupt to PS Interrupt Controller, and Reset Reorganized and expanded Chapter 9, DMA Controller. Added 10.1.3 Notices, expanded 10.1.6 1/0 Signals, added 10.6. 11 DRAM Write Latency Restriction, 10.8.1 ECC Initialization, 10.8.4 ECC Programming Model, and 10.9.1 Operating Modes Added 12.2.4 I/O Mode Considerations and updated 12.3.5 RX/Tx FIFO Response to I/O Command Sequences. Reworked 16.3.3 1/0 Configuration, added 16.4 IEEE 1588 Time Stamping and 16.6.7 Mio Pin Considerations Added 18.2.7 CANo-to-Canl Connection. Expanded 19.1 Introduction, 19.1.3 Notices, and Table 19-1. Added Receiver Timeout mechanism, updated Figure 19-7. Added 19.2.9 UarTo-to-UARTl Connection and 19.2.10 Status and Interrupts, expanded 19.2. 11 Modem Control, reworked 19.3 Programming Guide and 19.4.2 Resets Added 20 2.7 I2C0-to-I2C1 Connection. Added 21.1.2 PL Resources by Device Type, Voltage Level Shifters and reorganized content of chapter 21, programmable logic description Added 25.7.1 Clock Throttle Expanded 26.4.1 PL General Purpose User Resets. Updated register database in sections B 3 Module Summary through B 34 USB Controller(usb in Appendix B 11/16/2012 1.4 Changed second bullet under NAND Flash Interface from "Up to a 4 gB device"to"Up to a 1 gb device"in Chapter 11, Static Memory Controller Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(v1.11) September 27, 2016 Date Version Revision 03/07/2013 1.5 Added 7z100 device and made minor clarifications to Chapter 1, Introduction Made minor clarifications to Chapter 2, Signals, Interfaces, and Pins, Chapter 3, Application Processing Unit, Chapter 4, System Addresses, and Chapter 5, Interconnect Clarified section 6.1 Introduction and other sections and added Ps independent jTAG Non-Secure Boot section in Chapter 6, Boot and Configuration. Made minor clarifications to Chapter 7, Interrupts, Chapter 8, Timers, Chapter 9, DMA Controller, Chapter 10, DDR Memory Controller, Chapter 11, Static Memory Controller, and Chapter 12, Quad-SPI Flash Controller. Expanded 12.2 Functional Description in Chapter 12, Quad-SPI Flash Controller Made minor clarifications to Chapter 13, SD/SDIO Controller Made major clarifications/updates to Chapter 14, General Purpose I/O(GPIO). Reworked and expanded Chapter 15, USB Host, Device, and OTG Controller. Made minor clarifications to Chapter 16, Gigabit Ethernet Controller Reworked and expanded chapter 17 SPl Controller made minor clarifications to Chapter 18, CAN Controller, and Chapter 19, UART Controller Made major clarifications/updates to Chapter 20, I2C Controller(added new sections, 20.3 Programmer's Guide, 20.4 System Functions, and 20.5 I/O Interface). Made minor clarifications to Chapter 21, Programmable Logic Description and added new sections 21. 1.2 PL Resources by Device Type and 21.1.3 Notices Made minor clarifications to Chapter 22, Programmable logic Design Guide and Chapter 23, Programmable Logic Test and Debug. Reworked and expanded Chapter 24, Power Management Made minor clarifications to Chapter 25, Clocks, Chapter 26, Reset System, Chapter 27, JTAG and DAP Subsystem, Chapter 28, System Test and Debug, and chapter 29, On-Chip Memory (OCM). Reworked and expanded Chapter 30, XADC Interface Made minor clarifications to Chapter 31, PCI Express Reworked and expanded Chapter 32, Device Secure Boot. Updated Appendix A, Additional Resources. Updated register database in sections B 3 Module Summary through B 34 USB Controller(usb)in Appendix B 06/28/2013 1.6 Added icons where applicable. Enhanced first sentence under Quad-SPI Controller in c Clarified first paragraph, added step 2, and clarified step 5 in section 2. 4 PS-PL Voltage Level shifter Enables. Changed drive strength "to"slew rate"in section 2.5.7 MIO Pin Electrical Parameters. Added second sentence and updated Table 2-11 in section 2.7.4 Idle AXI, dDR Urgent/Arb, SRAM Interrupt Signals. Corrected note 4 in table 4-1 and table 4-2. made minor clarifications and added new rsa authentication time section to Chapter 6, Boot and Configuration Made minor clarifications to sections 7.2.2 CPU Private Peripheral Interrupts(PPI)and 7.2.3 Shared Peripheral Interrupts (SPD), and updated Table 7-4 and Table 7-5. Clarified first row in Table 9-12. Added tip to section 10.4.3 Aging Counter, added sentence to Write Leveling, and step 2 in section 10.9.2 Changing Clock Frequencies, and moved section 10.9.6 DDR Power Reduction from Chapter 24, Power Management to this chapter Added tip to section 11.2.2 Clocks. Added Table 12-8. Added MMC3, 31 standard information to section 13.1 Introduction. Added step 6 to section 14.3.1 Start-up Sequence, added section 14.3.5 GPIO as Wake-up Event, added second paragraph to 14.4.1 Clocks. Added section 16.7 Known Issues Added note to 17.4.2 Clocks. Changed value of 107 Mb to 140 Mb in second sentence under section 21.4 Configuration. Added values for the 7z100 device in Table 21-2 Clarified first paragraph in section 24. 2.2 PL Power-down Control and updated table 24-2. added note to section 25.6.1 USB Clocks clarified second paragraph in section 25. 10.4 PLLs, and added sentence to steps 2 and 3 in Software-Controlled PLL Update section. Changed"RESET_REASON"to REBOOT_ STATUS in section 26. 2.3 System Software Reset, added section 26.5 Register Overview, deleted first two rows from table 26-2 and modified last paragraph in section 26.5.1 Persistent Registers. Clarified section 29.1 Introduction, added three paragraphs to Starvation Scenarios section, and added 29.2.5 Address Mapping heading Corrected spelling of"MCTRL""MCTL" in sections 30.4 Programming Guide for the PS-XADC Interface and 30.7.2 resets Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback 4 UG585(v1.11) September 27, 2016 Date Version Revision 06/28/2013 1.6 Added section 31.5 Root Complex Use Case. Added FIPS standards and clarified section (Cont d)32.1.2 Features, updated configuration file and secure boot process steps in Figure 32-1, added boot time penalty to Power on Reset section, changed"Secure Boot heading to" Secure FSBL Decryption", changed"ROM code to "OCM ROM Memory"in Figure 32-2 and "ROM to" OCM ROM"in Table 32-3, updated sections 32 2.7 Boot Image and Bitstream Decryption and Authentication, 32. 2. 8 HMAC Signature, 32 2.9 AES Key Management, 32.3.1 Non-Secure Boot State, 32.3.4 Boot Partition Search, and 32.3.7 Secure Boot Modes of Operation(deleted Table 32-4, Non-secure Boot Options"). Updated register database in sections B3 Module Summary througl B34 USB Controller(usb) in Appendix B 02/11/2014 1.7 Added 7z015 device, updated device notices and made minor clarifications throughout document(denoted with change bars). Added section 3. 10 Implementation-Defined Configurations. Added sections 5.7 Loopback and 5.8 Exclusive AXI Accesses Reworked Chapter 6, Boot and Configuration. Added section 7.2.4 Interrupt Sensitivity, Targeting and Handling. Added sections 8.4.6 Clock Input Option for SWDT and 8.5.6 Clock Input Option for Counter/Timer. Updated section 10.7 Register Overview. Added section 11.7 NOR Flash Bandwidth Added sections AXI Read Command Processing and 12.2.7 Supported Memory Read and Write Commands. Added section 16.1.4 Clock Domains and reworked section 16.7 Known Issues (previously titled"Limitations Updated section 21.1.2 PL Resources by Device Type and added section 21.3.4 GTP Low-Power Serial Transceivers. Added Peripheral Clock Gating subsection Updated through B 34 USB Controller(usb) in Appenax ase in sections B 3 Module Summary Table 26-1 and Table 26-4. Updated register databa 09/16/2014 1.8 Added position information for available device and package combinations for the signals associated with each gt serial transceiver channel to sections 213 3 GTX LoW-Power Serial Transceivers and 213.4 GTP Low-Power Seria Transceivers 09/19/2014 1.8.1 Removed erroneous banner from Chapter 21, Programmable Logic Description Corrected send feedback button clarity issue in footers 11/17/2014 1.9 Added 7z035 device, updated device notices, and made minor clarifications throughout document (denoted with change bars) 11/19/2014 1.9.1 Corrected document date 02/23/2015 1.10 Added clarification on the timing relationship between pl power up and the ps POR reset signal to section 2.2 Power Pins and section 6.3.3 BootROM Performance PS por b De-assertion guidelines 09/27/2016 1.11 Added 7z007s, 7z012s, and 7z014s single-core devices and updated the respective device notices throughout document(denoted with change bars). Updated Figure 2-1, Table 21-1, and Table 21-2 Updated device codes in Register PSS_IDCODE Details Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(v1.11) September 27, 2016 &A XILINX Table of contents Chapter 1: Introduction 1.1 Overview∴ 鲁:鲁 26 1.1.1 Block Diagram ,,27 11.2 Documentation resources ,: ,,28 1.1.3 Notices 30 1.2 Processing System(PS)Features and descriptions 31 1.2.1 Application Processor Unit(APU ,,31 1.2.2 Memory Interfaces 32 1.2.3 1/0 Peripherals 34 1.3 Programmable Logic Features and descriptions .38 1.4 Interconnect Features and description 39 1.4.1 PS Interconnect Based on AXI High Performance Datapath Switches 39 1.42 PS-PL Interfaces 40 1.5 System Software 41 Chapter 2: Signals, Interfaces, and pins 2.1 Introduction 42 2.11 Notices 42 2.2 Power pins...,,,,,,,,,,,,,,,,, 44 2. 3 PS l/O Pins..,.,...... 45 2.4 PS-PL Voltage Level Shifter Enables ,,,,,46 2.5 PS-PL MIO-EMIO Signals and Interfaces 47 2.5.1 1 0 Peripheral(lOP) Interface Routing 47 2.5.2 OP Interface Connections 48 2.5.3 MIO Pin Assignment Considerations 50 2.5.4 MIO-at-a-Glance Table 52 2.5.5 MIO Signal Routing 53 2.5.6 Default Logic Level ··.··:··.:·········:··.·,· 53 25.7 MIO Pin electrical parameters 54 2.6 PS-PL AXI Interfaces .:...···...······ 55 2.7 PS-PL Miscellaneous signals 55 2.7.1 Clocks and resets 56 2.7.2 Interrupt Signals 57 2.7.3 Event signals 57 2.7.4 Idle AXl, DDR Urgent/Arb, SRAM Interrupt Signals 57 2.7.5 DMA Req/Ack Signals 58 2.8 PL l/O Pins 58 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(v1.11) September 27, 2016 &A XILINX Chapter 3: Application Processing Unit 3.1 Introduction..,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,,..,60 3. 1.1 Basic Functionality 60 3.1.2 System-Level view 62 3.2 Cortex-A9 Processors 64 3.2.1 Summary 64 3. 2.2 Central Processing Unit(CPU) 64 3.2.3Leve|1 Caches,,,,,,,, 67 3.2.4 Memory ordering ,,70 3.2.5 Memory Management Unit(MMU) 3.2.6 Interf 88 3.2.7 NEON 89 3.2.8 Performance Monitoring Unit 90 3.3 Snoop Control Unit(SCU) ,,,,,,,.,..90 3.3.1 Summary 90 3.3.2 Address Filtering 91 3.3.3 SCU Master ports 91 3. 4 L2-Cache ∴,,,,,,,∴,∴...92 3. 4.1 Summary 92 3.4.2 Exclusive L2-L1 Cache Configuration 95 3.4.3 Cache Replacement Strategy 3, 4,4 Cache lockdown ,,,,96 3.4.5 Enabling and disabling the l2 Cache Controller ,98 3.4.6 RAM Access Latency Control 98 3.4.7 Store Buffer Operati 98 3.4.8 Optimizations between Cortex-A9 and L2 Controller ,99 3.4.9 Pre-fetching Operation 100 3.4.10 Programming model ,,,,,,,,,,,,,,,,,,,,,,101 3.5 APU Interfaces,,,,,,,,,,,,,,,,,,,,,,, ■■■ 。,,,,,,,,,.103 3.5.1 PL Co-processing Interfaces ,,,,,,,,,,,,103 3.5.2 Interrupt Interface ,,,,,106 3.6 Support for trustZone..........,......... 107 3.7 Application Processing Unit(APU)Reset............... 107 3.7.1 Reset Functionality... 107 3.7.2 APU State After reset 108 3.8 Power considerations.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,108 3.8. Introduction .108 3.8.2 Standby Mode 109 3.8.3 Dynamic Clock Gating in the L2 Controller ..,,110 3.9 CPU Initialization Sequence........,............,...... 110 3.10 Implementation-Defined Configurations..,..........,....... 111 Chapter 4: System Addresses 4.1 Address Map 112 4.2 System Bus Masters 114 4.3 SLCR Registers .,,,,,,....114 4.4 CPU Private Bus registers 115 4.5 SMC Memory ,,,,,,,.,..115 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(v1.11) September 27, 2016 &A XILINX 4.6 PS I/O Peripherals 116 4.7 Miscellaneous ps registers...............................116 Chapter 5: Interconnect 5.1 Introduction 118 5.1.1F6 118 5.1.2 Block Diagram 119 5.1.3 Datapaths 121 5.1.4 Clock domains 122 5.1.5 Connectivity 125 5.1.6AⅪ|D.. ,,,125 5.1.7 Read/ Write Request capability ,,,,,,,,,,126 5.1.8 Register Overview 126 5.2 Quality of Service(Qos)........... 127 5.2.1 Basic Arbitration 127 5.2.2 Advanced qos ,,,,,,,,127 5.2.3 DdR Port arbitration 128 5.3 AXI HP Interfaces ,。,,,。,。,128 5.31 Feat 128 5.3.2 Block Diagram 129 5.3.3 Functional Description 130 5,3. 4 Perfo 130 5.3.5 Register Overview 131 5.3.6 Bandwidth Management Features 131 5.3.7 Transaction Types 135 5.3. 8 Command Interleaving and Re-Ordering 135 5.3.9 Performance Optimization Summary 136 5.4 AXI ACP Interface 。137 5.5 AXI GP Interfaces 138 5.5.1 Features .138 5.5.2 Performance 138 56Ps-PLAⅪ nterface Signals.…,138 5.6.1 AXI Signals...... ,,,,,,,,,,,,,,,,,,,138 5.6.2 AXI Clocks and resets 142 5.7 Loopback :· 143 5.8 Exclusive axl Accesses ,。,..144 5.81CPU/L2 ··::· ,144 5.8.2 ACP 145 5.8.3 DDRC 145 5.8. 4 System Summary 147 Chapter 6: Boot and configuration 6.1 Introduction。,,,,,,,,,,。,,,,,,,, ,,,。,148 6. 1.1 PS Hardware Boot stages 152 6.1.2 PS Software Boot Stages ....152 6.1.3 Boot device content .153 6. 1. 4 Boot modes 153 6.1.5 BootRoM Execution 154 6.1.6 FSBL/User Code Execution ,,155 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(v1.11) September 27, 2016 &A XILINX 6.1.7 pl Boot process 156 6.1.8 PL Configuration Paths 156 6. 1.9 Device Configuration Interface ......158 6. 1.10 Starting Code on CPu 1 160 6.1.11 Development environment 160 52 Device start-唧p.∴∴∴ 161 6.2.1 Introduction 161 6.2.2 Power requirements 6.2.3 Clocks and plls ,,,162 6.2. 4 Reset Operations ,,,,,,,,162 6.2.5 Boot Mode pin Settings 165 6.2.6 l/0 Pin Connections for Boot Devices 166 6.3 BootROM 167 63.1 BootRoM flowchart,,,,,,,,,,,,,,,,,,, ,,,,,,,,167 6.3.2 BootRoM Header .,170 6.3.3 BootROM Performance 175 6.3.4 Quad-SPI Boot 179 6.3.5 NAND Boot,,,,,,,,,, 182 6.3.6 noR Boot 185 6.3.7 SD Card Boot ,,,,,,,,,,,,,187 6.3.8 TAG Boot 188 6.3.9 Reset Boot and lockdown states 192 6.3.10 BootRoM Header search ,,194 6.3.11 MultiBoot 195 6.3.12 BootROM Error codes ,,,197 6313 Post bootrom State .......201 6. 3. 14 Registers Modified by the bootRoM-Examples ,,,203 6.4 Device Boot and PL Configuration......,................. 204 6. 4.1 PL Control via PS Software ·:.::.·· 205 6.4.2 Boot Sequence EXamples :: 206 6.4.3 PCAP Bridge to PL ..,.211 6.4.4 PCAP Datapath Configurations ,,,,,,,,213 6.4.5 PL Control via user-jTAg 217 6.5 Reference section 219 6.5.1 PL Configuration Considerations ,,219 6.5.2 Boot time ref 220 6.5.3 Register Overview 222 6. 5, 4 PS Version and device revision 223 Chapter 7: Interrupt 7.1 Environment,,,,,,,,。,。,,。 224 7. 1.1 Private, Shared and software Interrupts 225 7.1.2 Generic Interrupt Controller(GIC) 225 7.1.3 Resets and Clocks 225 7.1.4 Block Diagram 225 7.1.5 CPU Interrupt Signal Pass-through 226 7.2 Functional description 227 7. 2.1 Software Generated Interrupts (sGl).......... 227 7. 2.2 CPU Private Peripheral Interrupts(PPl) ,,,,,,,228 7.2.3 Shared Peripheral Interrupts (sPl) 228 7. 2. 4 Interrupt Sensitivity, Targeting and handling 230 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(v1.11) September 27, 2016 &A XILINX 7.2.5 Wait for Interrupt Event Signal (WFl) 232 7.3 Register Overview........ ,,232 7.3 1 Write protection lock 233 74Pr。 gramming Model.,… 234 7. 4.1 Interrupt prioritization ,,234 7.4.2 Interrupt Handling 234 7.4.3 ARM Programming Topics 235 7.4.4 Legacy Interrupts and security Extensions .235 Chapter 8: Time 8.1 Introduction 236 8.1.1 System Diagram 237 8.1.2 Notices 237 8.2 CPU Private Timers and Watchdog timers.................... 238 8.2.1 Clocking ,,,,,,,,,,,,,,,,,,,,,,238 8.2.2 Interrupt to ps Interrupt Controller 238 8.2.3 Resets..,,,, 238 8.2.4 Register Overview 238 8.3 Global Timer GT).............................. 239 8.3.1 Clocking 239 8.3.2 Register Overview 239 84 System Watchdog Timer(SWDT.……240 8. 41 Feat 240 8.4.2 block diagra .241 8.4.3 Functional Description 241 8.4.4 Register Overview.....,,,,,,,,,,,,,,,,,,,,,,, 242 8.4.5 Programming Mode 243 8.4.6 Clock Input Option for SWDt 243 8.4.7 Reset Output Option for SWDT ,,243 8.5 Triple Timer Counters(TTc ······· 244 8.5.1 Features 244 8.5.2 Block Diagram ,,244 8.5.3 Functional Description.......... .,,,,,,,,,,,,,,,,,,245 8.5.4 Register Overview ,,,,,,,,,,,,,,,,,,,,246 8.5.5 Programming Model 247 8.5.6 Clock Input Option for Counter /Timer 248 86l/ O Signals..,,,,,,249 Chapter 9: DMA Controller 9.1 Introduction。,,,,,,,。,,,,。,,,,,,,,,,,,。。。,, ,,,。250 9.1.1 Features 251 9.1.2 System Viewpoint 252 9.1.3 Block Diagram 253 9.1 4 Notice 255 9.2 Functional description 256 9.2.1 DMA Transfers on the axi Interconnect ,,,,,,,,,,,257 9.2.2 AXI Transaction Considerations 259 9.2.3 DMA Manager. 259 9.2.4 Multi-channel Data FIFO (MFIFO) 261 Zynq-7000ApSocTechnicalReferenceManualwww.xilinx.com Send feedback UG585(v1.11) September 27, 2016

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