ADI ADSP-BF532:400 MHz高性能Blackfin处理器英文产品数据手册.pdf

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ADI ADSP-BF532:400 MHz高性能Blackfin处理器英文产品数据手册pdf,ADI ADSP-BF532:400 MHz高性能Blackfin处理器英文产品数据手册
DSP-BF531/ADSP-BF532/ADSP-BF533 GENERAL DESCRIPTION The ADSp-BF531/ADSP-BF532/ADSP-BF533 processors are power consumption. Varying the voltage and frequency can members of the Blackfin family of products, incorporating the result in a substantial reduction in power consumption,com Analog Devices, Inc /Intel Micro Signal Architecture(MSa pared with just varying the frequency of operation. This Blackfin processors combine a dual-MAC state-of-the-art signal translates into longer battery life for portable appliances processing engine, the advantages of a clean, orthogonal RISC like microprocessor instruction set, and single instruction, mul SYSTEM INTEGRATION tiple data(SIMD)multimedia capabilities into a single The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are instruction set architecture highly integrated system-on-a-chip solutions for the next gener- The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are ation of digital communication and consumer multimedia completely code and pin-compatible, differing only with respect applications By combining industry-standard interfaces with a to their performance and on-chip memory specific perfor- high performance signal processing core, users can develop mance and memory configurations are shown in Table 1 cost-effective solutions quickly without the need for costl external components. The system peripherals include a UART Table 1. Processor Comparison port, an SPI port, two serial ports(SPORTs), four general-pur pose timers(three with PWM capability), a real-time clock, a watchdog timer, and a parallel peripheral interface PROCESSOR PERIPHERALS Features 出是2 The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con- tain a rich set of peripherals connected to the core via several SPORTS 2 high bandwidth buses, providing flexibility in system config UART tion as well as excellent overall system performance(see the fa SPI functional block diagram in Figure l on Page 1). The general GP Timers 3 3 purpose peripherals include functions such as UART, timers Watchdog timers vith Pwm(pulse-width modulation) and pulse measurement capability, general-purpose 1/O pins, a real-time clock, and a RTC watchdog timer. This set of functions satisfies a wide variety of Parallel Peripheral Interface 1 typical system support needs and is augmented by the system GPIOs 16 16 16 expansion capabilities of the part. In addition to these general o L1 Instruction SRAM/Cache 16k bytes 16K bytes 16K bytes urpose peripherals, the processors contain high speed serial L1 Instruction sram 16K bytes 32K bytes 64K bytes and parallel ports for interfacing to a variety of audio, video, and modem codec functions; an interrupt controller for flexible L1 Data SRAM/Cache 16K bytes 32K bytes bytes management of interrupts from the on-chip peripherals or o L1 Data sram 32K bytes external sources; and power management control functions to L1 Scratchpad 4K bytes 4K bytes 4K bytes tailor the performance and power characteristics of the proces E L3 Boot rom 1 k bytes 1 k bytes 1K bytes sor and system to many application scenarios All of the peripherals, except for general-purpose T/O, real-time Maximum Speed Grade 400 MHz 400 MHz 600 MHz clock, and timers, are supported by a flexible DMa structure Package options: There is also a separate memory dma channel dedicated to CSP BGA 160-Ba160-Ba160-Ball data transfers between the processor's various memory spaces Plastic BGa 169-Ba169-Bal169-Bal including external SDRAM and asynchronous memory. Multi LQFP 176-Lead176-Lead 176-Lead ple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activ By integrating a rich set of industry-leading system peripherals ity on all of the on-chip and external peripherals and memory, Blackfin processors are the platform of choice for The processors include an on-chip voltage regulator in support next generation applications that require RISC-like program of the processors dynamic power management capability The mability, multimedia support, and leading-edge signal voltage regulator provides a range of core voltage levels from processing in one integrated package VrDEXT. The voltage regulator can be bypassed at the users discretion PORTABLE LOW POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management-the ability to vary both the volt age and frequency of operation to significantly lower overall F Page 3 of 64 November 2008 ADSP-BF531/ADSP-BF532/ADSP-BF533 BLACKFIN PROCESSOR CORE In addition, multiple ll memory blocks are provided, offering a As shown in Figure 2 on Page 5, the Blackfin processor core configurable mix of SRAM and cache. The memory manage- contains two 16-bit multipliers, two 40-bit accumulators, two ment unit (MMU) provides memory protection for individual 40-bit ALUs, four video ALUs, and a 40-bit shifter The compu- tasks that may be operating on the core and can protect system tation units process 8-bit, 16-bit, or 32-bit data from the registers from unintended access register file The architecture provides three modes of operation: user mode, The compute register file contains eight 32-bit registers. When supervisor mode, and emulation mode User mode has performing compute operations on 16-bit operand data, the restricted access to certain system resources, thus providing a register file operates as 16 independent 16-bit registers. All protected software environment, while supervisor mode has unrestricted access to the system and core resources operands for compute operations come from the multiported register file and instruction constant fields The Blackfin processor instruction set has been optimized so Each MAC can perform a 16-bit by 16-bit multiply in each that 16-bit opcodes represent the most frequently used instruc cycle, accumulating the results into the 40-bit accumulators tions, resulting in excellent compiled code density Complex Signed and unsigned formats, rounding, and saturation are DSP instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors supported support a limited multi-issue capability, where a 32-bit instruc- The ALUs perform a traditional set of arithmetic and logical tion can be issued in parallel with two 16-bit instructions operations on 16-bit or 32-bit data. In addition, many special allowing the programmer to use many of the core resources in a instructions are included to accelerate various signal processing single instruction cycle tasks. These include bit operations such as field extract and population count, modulo 2multiply, divide primitives,satu The Blackfin processor assembly language uses an algebraic syn ration and rounding, and sign/exponent detection. The set of tax for ease of coding and readability. The architecture has been optimized for use in conjunction with the C/C++ compiler, video instructions includes byte alignment and packing opera- tions, 16-bit and 8-bit adds with clipping, 8-bit average resulting in fast and efficient software implementations operations, and 8-bit subtract/absolute value/accumulate(SAA MEMORY ARCHITEC TURE operations. Also provided are the compare/select and vector search instructions The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view memory as a single unified 4G byte address space using 32-bit For certain instructions, two 16-bit alU operations can be per addresses. All resources, including internal memory external formed simultaneously on register pairs(a 16-bit high half and memory, and I/O control registers, occupy separate sections of 16-bit low half of a compute register). Quad 16-bit operations this common address space. The memory portions of this are possible using the second alU address space are arranged in a hierarchical structure to provide The 40-bit shifter can perform shifts and rotates and is used to a good cost/performance balance of some very fast, low latency support normalization, field extract, and field deposit on-chip memory as cache or SRAM, and larger, lower cost and instructions performance off-chip memory systems. See Figure 3, Figure 4 The program sequencer controls the flow of instruction execu and Figure 5 on Page 6. tion, including instruction alignment and decoding For The L1 memory system is the primary highest performance program flow control, the sequencer supports PC relative and memory available to the Blackfin processor. The off-chip mem indirect conditional jumps(with static branch prediction), and ory system, accessed through the external bus interface unit subroutine calls. Hardware is provided to support zero-over (EBIU, Provides expansion with SDRAM, flash memory, and head looping. The architecture is fully interlocked, meaning that SRAM, optionally accessing up to 132M bytes of the programmer need not manage the pipeline when executing physical memory. instructions with data dependencies The memory DMA controller provides high bandwidth data The address arithmetic unit provides two addresses for simulta movement capability. It can perform block transfers of code or neous dual fetches from memory. It contains a multiported data between the internal memory and the external register file consisting of four sets of 32-bit index, modify memory spaces length, and base registers(for circular buffering), and eight additional 32-bit pointer registers(for C-style indexed stack Internal(On-Chip)Memory manipulation) The processors have three blocks of on-chip memory that pro Blackfin processors support a modified Harvard architecture in vide high bandwidth access to the core combination with a hierarchical memory structure. Level 1(Ll) The first block is the Ll instruction memory, consisting of up to memories are those that typically operate at the full processor 80k bytes SRAM, of which 16k bytes can be configured as a speed with little or no latency. At the Ll level, the instruction four way set-associative cache. This memory is accessed at full memory holds instructions only. The two data memories hold processor data, and a dedicated scratchpad data memory stores stack and local variable information F Page 4 of 64 November 2008 DSP-BF531/ADSP-BF532/ADSP-BF533 ADDRESS ARITHMETIC UNIT 3 L2 L1 DAG1 0 LO DA0,32 PO RAB PREG LD STAT SEQUENCER R7.HIR7 R6.H R6. L R5.H 16 ALIGN R4.L R3. H[R3.L R2.H R2. L DECODE R1 11.L BARREL ROHRO.L SHIFTER 40 40 LOOP BUFFER AO A1 CONTROL 32 DATA ARITHMETIC UNIT Figure 2. Blackfin Processor Core The second on-chip memory block is the Ll data memory, con IM byte segment regardless of the size of the devices used,so sisting of one or two banks of up to 32K bytes. The memor that these banks are only contiguous if each is fully populated banks are configurable, offering both cache and SraM func- with iM byte of memory tionality. This memory block is accessed at full processor speed 10 Memory Space The third memory block is a 4K byte scratchpad SRAM, which runs at the same speed as the Ll memories, but is only accessible Blackfin processors do not define a separate I/O space. all as data SRaM and cannot be configured as cache memory resources are mapped through the flat 32-bit address space On-chip i/o devices have their control registers mapped into External (off-Chip)Memory memory mapped registers(MMRs)at addresses near the top of External memory is accessed via the external bus interface unit the 4G byte address space. These are separated into two smaller (EBIU). This 16-bit interface provides a glueless connection to a blocks, one containing the control MMRs for all core functions bank of synchronous DRAM (SDRAM)as well as up to four and the other containing the registers needed for setup and con banks of asynchronous memory devices including flash, trol of the on-chip peripherals outside of the core. The mmrs EPROM, ROM, SRAM, and memory mapped I/O devices are accessible only in supervisor mode and appear as reserved space to on-chip peripheral The PC133-compliant sdraM controller can be programmed to interface to up to 128M bytes of Sdram. The sdram con Booting troller allows one row to be open for each internal SDRAM The ADSP-BF531/ADSP-BF532/ ADSP-BF533 processors con bank, for up to four internal SDRAM banks, improving overall tain a small boot kernel, which configures the appropriate system performance peripheral for booting. If the processors are configured to boot The asynchronous memory controller can be programmed to from boot rOM memory space, the processor starts executing control up to four banks of devices with very flexible timing from the on-chip boot ROM. For more information, see Boot- parameters for a wide variety of devices. Each bank occupies a ing modes on Page 14 Page 5 of 64 November 2008 ADSP-BF531/ADSP-BF532/ADSP-BF533 0 XFFFF FFFF一 OXFFFF FFFF CORE MMR REGISTERS (2M BYTE CORE MMR REGISTERS (2M BYTE 0xFFE00000 0XFFE00000 SYSTEM MMR REGISTERS (2M BYTE) SYSTEM MMR REGISTERS(2M BYTE 0xFFc00000 0xFFc00000一 RESERVED RESERVED 0XFFB01000一 0XFFB01000一 SCRATCHPAD SRAM (4K BYTE) SCRATCHPAD SRAM (4K BYTE) OxFFB00000一 0xFFB00000 RESERVED RESERVED OXFFA14000一 0XFFA14000一 INSTRUCTION SRAM/CACHE (16K BYTE) INSTRUCTION SRAM/CACHE(16K BYTE) 0XFFA10000一 OxFFA10000 D RESERVED INSTRUCTION SRAM(64K BYTE) OXFFAD C000 0xFFA00000 INSTRUCTION SRAM(16K BYTE) RESERVED 0XFFA08000一 0xFF908000 RESERVED DATA BANK B SRAM/CACHE(16K BYTE) O2zu OxFFA0 000O oxFF904000 RESERVED DATA BANK B SRAM (16K BYTE) oXFF908000 0XFF900000一 RESERVED RESERVED 0xFF904000 oxFF808000 RESERVED DATA BANK A SRAM/CACHE (16K BYTE) 0xFF808000 0xFF804000 DATA BANK A SRAMCACHE(16K BYTE) DATA BANK A SRAM (16K BYTE) 0xFF804000 0XxFF800000 RESERVED RESERVED 0xEF000000一 oXEF000000 RESERVED RESERVED 0X20400000 0x20400000一 ASYNC MEMORY BANK 3(1M BYTE ASYNC MEMORY BANK 3(1M BYTE) 0x20300000 ox20300000 ASYNC MEMORY BANK 2(1M BYTE) ASYNC MEMORY BANK2(1M BYTE) 0x20200000 0x20200000一 ASYNC MEMORY BANK 1(1M BYTE) ASYNC MEMORY BANK 1(1M BYTE) 0x20100000 0x20100000一 ASYNC MEMORY BANK0(1M BYTE) ASYNC MEMORY BANK O(1M BYTE) 0x20000000 020000000一 RESERVED RESERVED 0x08000000 SDRAM MEMORY (16M BYTE TO 128M BYTE) SDRAM MEMORY(16M BYTE TO 128M BYTE 0x00000000 0xoo000000— Figure 3. ADSP-BF531 Internal/External Memory Map Figure 5. ADSP-BF533 Internal/External Memory Map OxFFFF FFFF Event Handling CORE MMR REGISTERS(2M BYTE 0xFFE00000 The event controller on the processors handle all asynchronous SYSTEM MMR REGISTERS(2M BYTE) OXFFC0 000 and synchronous events to the processor. The ADSP-BF531 RESERVED OxFFB0 1000 ADSP-BF532/ADSP-BF533 processors provide event handling SCRATCHPAD SRAM(4K BYTE) that supports both nesting and prioritization. Nesting allows OxFFB0 0000 RESERVED multiple event service routines to be active simultaneously. Pri- 0xFFA14000 oritization ensures that servicing of a higher priority event takes INSTRUCTION SRAM/CACHE (16K BYTE OxFFA1 0000 precedence over servicing of a lower priority event. The control- INSTRUCTION SRAM(32K BYTE) ler provides support for five different types of events OxFFA0 8000 RESERVED Emulation- An emulation event causes the processor to 0xFFA00000 RESERVED enter emulation mode allowing command and control of OxFF90 8000 the processor via the jtag interface DATA BANK B SRAM/CACHE(16K BYTE) oxFF904000 RESERVED Reset- This event resets the processor oxFF808000 DATA BANK A SRAM/CACHE(16K BYTE) Nonmaskable Interrupt(NMI)-The NMi event can be oxFF804000 generated by the software watchdog timer or by the NMi RESERVED 0xEF000000 input signal to the processor. The NMi event is frequently RESERVED 0x20400000 used as a power-down indicator to initiate an orderly shut ASYNC MEMORY BANK 3 (1M BYTE) down of the system 0x20300000 ASYNC MEMORY BANK 2 (1M BYTE) Exceptions -Events that occur synchronously to program 020200000 ASYNC MEMORY BANK 1(1M BYTE) flow (i.e, the exception is taken before the instruction is 0x20100000 allowed to complete). Conditions such as data alignment ASYNC MEMORY BANKO(1M BYTE 0x20000000 violations and undefined instructions cause exceptions RESERVED 0x08000000 Interrupts- Events that occur asynchronously to program SDRAM MEMORY (16M BYTE TO 128M BYTE) x00000000 flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction Figure 4. ADSP-BF532 Internal/ External Memory Map F Page 6 of 64 November 2008 DSP-BF531/ADSP-BF532/ADSP-BF533 Each event type has an associated register to hold the return Table 3. System Interrupt Controller(SIC) address and an associated return-from-event instruction When an event is triggered, the state of the processor is saved on the Peripheral Interrupt Event Default Mapping supervisor stack PLL Wakeup IVG7 The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors event DMA Error IVG7 controller consists of two stages, the core event controller(CeC) PPI Error IVG and the system interrupt controller(SIC). 'The core event con SPORT O Error ∨G7 troller works with the system interrupt controller to prioritize SPORT 1 Erro and control all system events. Conceptually interrupts from the peripherals enter into the SIC, and are then routed directly into SPI Error ⅣVG7 the general-purpose interrupts of the Cec UART Error ⅣVG7 Real-Time Clock Core Event Controller(cec) DMA Channel O(PPl) ⅣVG8 The CEC supports nine general-purpose interrupts(IVG15-7) DMA Channel 1(SPORT O Receive) ∨G9 in addition to the dedicated interrupt and exception events Of these general-purpose interrupts, the two lowest priority inter DMA Channel 2(SPORT O Transmit rupts(IVG15-14)are recommended to be reserved for software DMA Channel 3(SPORT 1 Receive ∨G9 interrupt handlers, leaving seven prioritized interrupt inputs to DMA Channel 4(SPORT 1 Transmit IVG9 support the peripherals of the processor. Table 2 de escribes the DMA Channel 5 (SPD) IVG10 inputs to the CeC, identifies their names in the event vector DMA Channel 6 (UART Receive IVG10 table(EvT), and lists their priorities DMA Channel 7 (UArT Transmit) IVG10 Table 2. Core Event Controller (Cec) ⅣVG11 Timer 1 1VG11 Priority Timer 2 ∨G11 (O is Highest) Event class EVT Entry Port F GPlO Interrupt A ⅣVG12 Emulation/Test Control EMU Port F GPlo Interrupt B ⅣVG12 Reset Nonmaskable Interrupt NMI Memory dMA Stream O ⅣVG13 Memory dma stream 1 ⅣG13 Exception EVX Software Watchdog timer IVG13 Reserved Hardware Error THW Event Control 6 Core timer ITMR The processors provide a very flexible mechanism to control the General Interrupt 7 ⅣVG7 processing of events. In the CEC, three registers are used to 8 General Interrupt 8 coordinate and control events. Each register is 32 bits wide General Interrupt 9 IG9 CEC interrupt latch register(ILAT)-The ILAT register 10 General Interrupt 10 IVG10 indicates when events have been latched. The appropriate General Interrupt 11 bit is set when the processor has latched the event and 12 General Interrupt 12 IVG12 cleared when the event has been accepted into the system This register is updated automatically by the controller,but 13 General Interrupt 13 IG13 it can also be written to clear( cancel) latched events This 14 General Interrupt 14 VG14 register can be read while in supervisor mode and can only General Interrupt 15 IVG15 be written while in supervisor mode when the correspond g mAsK bit is cleared System Interrupt Controller (SIC) CEC interrupt mask register(IMASK)-The IMASK regis The system interrupt controller provides the mapping and rout- ter controls the masking and unmasking of individual ing of events from the many peripheral interrupt sources to the events. When a bit is set in the mask register that event is prioritized general-purpose interrupt inputs of the CEC unmasked and is processed by the CEC when asserted A Although the processors provide a default mapping, the user cleared bit in the mask register masks the event, can alter the mappings and priorities of interrupt events by writ preventing the processor from servicing the event even ing the appropriate values into the interrupt assignment though the event may be latched in the ilat register. This registers(SIC IARx). Table 3 describes the inputs into the SIC register can be read or written while in supervisor mode. and the default mappings into the cel Page 7 of 64 November 2008 ADSP-BF531/ADSP-BF532/ADSP-BF533 Note that general-purpose interrupts can be globally and the asynchronous memory controller. DMA-capable enabled and disabled with the sti and cli instructions peripherals include the SPOrTs, SPI port, UART, and PPI. Each respectively individual DMA-capable peripheral has at least one dedicated CEC interrupt pending register(IPEND)-The IPEND DMA channel register keeps track of all nested events. A set bit in the The DMa controller supports both 1-dimensional (l-D)and 2 IPEND register indicates the event is currently active or dimensional ( 2-D)DMA transfers dMa transfer initialization nested at some level. 'This register is updated automatically can be implemented from registers or from sets of parameters by the controller but can be read while in supervisor mode called descriptor blocks The siC allows further control of event processing by providing The 2-D DMA capability supports arbitrary row and column three 32-bit interrupt control and status registers. Each register sizes up to 64K elements by 64K elements, and arbitrary row contains a bit corresponding to each of the peripheral interrupt and column step sizes up to +32K elements. Furthermore the events shown in table 3 column step size can be less than the row step size, allowing SIC interrupt mask register(SIC_IMASK)-This register implementation of interleaved data streams This feature is controls the masking and unmasking of each peripheral especially useful in video applications where data can be interrupt event. When a bit is set in this register, that de-interleaved on the fl peripheral event is unmasked and is processed by the sys Examples of DMA types supported by the DMA controller tem when asserted. a cleared bit in this register masks the include. peripheral event, preventing the processor from servicing the event A single, linear buffer that stops upon completion A circular autorefreshing buffer that interrupts on each SIC interrupt status register(SIC_isr)- As multiple full or fractionally full buffer peripherals can be mapped to a single event, this register llows the software to determine which peripheral event 1-D or 2-D DMA using a linked list of descriptors source triggered the interrupt. A set bit indicates the 2-D DMA using an array of descriptors, specifying only the peripheral is asserting the interrupt, and a cleared bit indi base dMa address within a common page cates the peripheral is not asserting the event In addition to the dedicated peripheral DMA channels, there are SIC interrupt wakeup enable register(SIC_IWr)-By two pairs of memory DMA channels provided for transfers enabling the corresponding bit in this register, a peripheral between the various memories of the processor system. This can be configured to wake up the processor, should the enables transfers of blocks of data between any of the memo core be idled when the event is generated. See Dynamic ries-including external SDRAM, ROM, SRAM, and flash Power Management on Page ll memory-with minimal processor intervention. Memory DMA Because multiple interrupt sources can map to a single general transfers can be controlled by a very flexible descriptor-based purpose interrupt, multiple pulse assertions can occur simulta methodology or by a standard register-based autobuffer neously, before or during interrupt processing for an interrupt mechanism event already detected on this interrupt input. The IPENd reg REAL-TIME CLOCK ster contents are monitored by the sic as the interrupt acknowledgement The processor real-time clock(rto) provides a robust set of The appropriate ILAf register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The e gital watch features, including current time, stopwatch, and rm. The rtC is clocked by a 32.768 kHz crystal external to bit is cleared when the respective IPEND register bit is set. The the adsp-BF531/ADSP-BF532/ ADSP-BF533 processors. The ipend bit indicates that the event has entered into the proces RTC Peripheral has dedicated power supply pins so that it can sor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The essor is in a low power state. The rtC provides severe pro. remain powered up and clocked even when the rest of the pro- minimum latency from the rising edge transition of the programmable interrupt options, including interrupt per sec general-purpose interrupt to the ipend output asserted is three ond, minute, hour, or day clock ticks, interrupt on core clock cycles, however the latency can be much higher programmable stopwatch countdown or interrupt at a pro depending on the activity within and the state of the processor grammed alarm time The 32.768 kHz input clock frequency is divided down to a I h. DMA CONTROLLERS signal by a prescaler. The counter function of the timer consists The ADSP-BF531ADSP-BF532/ADSP-BF533 processors have of four counters a 60 second counter a 60 minute counter a 24 multiple, independent DMa channels that support automated hour counter, and a 32, 768 day counter. data transfers with minimal overhead for the processor core When enabled, the alarm function generates an interrupt when DMA transfers can occur between the processor's internal the output of the timer matches the programmed value in the memories and any of its DMA-capable peripherals. Addition alarm control register. The two alarms are time of day and a day ally, dma transfers can be accomplished between any of the and time of that day DMA-capable peripherals and external devices connected to the external memory interfaces, including the sdram controller F Page 8 of 64 November 2008 DSP-BF531/ADSP-BF532/ADSP-BF533 The stopwatch function counts down from a programmed clock the timer, or as a mechanism for measuring pulse widths value, with one second resolution When the stopwatch is and periods of external events. These timers can be synchro enabled and the counter underflows, an interrupt is generated nized to an external clock input to the PFl pin(TaClK),an Like other peripherals, the rtc can wake up the processor from external clock input to the PPi_clK pin(TmrClk), or to the sleep mode upon generation of any RtC wakeup event internal SclK Additionally, an RtC wakeup event can wake up the processor The timer units can be used in conjunction with the uart to from deep sleep mode, and wake up the on-chip internal voltage measure the width of the pulses in the data stream to provide an regulator from a powered-down state autobaud detect function for a serial channel Connect rIC pins RIXI and RTXO with external components The timers can generate interrupts to the processor core provid as shown in Figure 6 ing periodic events for synchronization, either to the system clock or to a count of external signa RTXI RIXO In addition to the three general-purpose programmable timers a fourth timer is also provided. This extra timer is clocked by the internal processor clock and is typically used as a system tick lock for generation of operating system periodic interrupts SERIAL PORTS (SPORTs The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors incorporate two dual-channel synchronous serial ports (SPORTO and SPORTI)for serial and multiprocessor commu- SUGGESTED COMPONENTS X1=ECLIPTEK EC3BJ(THROUGH-HOLE P ACKAGE)OR nications. The SPORTs support the following features EPSON MC405 12 pF LOAD (SURFACE-MO UNT PACKAGE IS capable operation Bidirectional operation- Each SPORT has two sets ofinde NOTE: C1 AND C2 ARE SPECIFIC TO CRY STAL SPECIFIED FOR X1 pendent transmit and receive pins, enabling eight channels CONTACT CRY STAL MANUFACTURER FOR DETAILS. CI AND C2 of i s stereo audio SPECIA CATIONS ASSUME BOARD TRACE CAP ACITANCE OF 3pF. Figure 6. External Components for rtC Buffered(8-deep) transmit and receive ports- Each por has a data register for transferring data words to and from WATCHDOG TIMER other processor components and shift registers for shifting data in and out of the data registers The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors include a 32-bit timer that can be used to implement a software Clocking- Each transmit and receive port can either use an watchdog function a software watchdog can improve system external serial clock or generate its own, in frequencies availability by forcing the processor to a known state througl ranging from(Isak/131,070) Hz to(fcx/2)Hz. generation of a hardware reset, nonmaskable interrupt (NMD) Word length-Each SPORT supports serial data words or general-purpose interrupt, if the le timer expires before being from 3 bits to 32 bits in length, transferred most-signifi- reset by software The programmer initializes the count value of cant-bit first or least-significant-bit first the timer, enables the appropriate interrupt, then enables the Framing- Each transmit and receive port can run with or timer. Thereafter, the software must reload the counter before it without frame sync signals for each data word. Frame sync counts to zero from the programmed value. This protects the signals can be generated internally or externally, active high system from remaining in an unknown state where software or low and with either of two pulse widths and early or late which would normally reset the timer, has stopped running due frame sync to an external noise condition or software error Companding in hardware- Each SPORT can perform If configured to generate a hardware reset, the watchdog timer A-law or u-law companding according to ITu recommen resets both the core and the processor peripherals. After a reset, dation G711. Companding can be selected on the transmit software can determine if the watchdog was the source of the and/or receive channel of the sport without additional hardware reset by interrogating a status bit in the watchdog latencies timer control register DMA operations with single-cycle overhead- Each SPORT The timer is clocked by the system clock (SCLK), at a maximum can automatically receive and transmit multiple buffers of equency o memory data. The processor can link or chain sequences of TIMERS DMA transfers between a sPort and memory There are four general-purpose programmable timer units in the adsp-BF531/ADSP-BF532/ADSP-BF533 processors. Three timers have an external pin that can be configured either as a pulse-width modulator(PWM)or timer output, as an input to Page 9 of 64 November 2008 ADSP-BF531/ADSP-BF532/ADSP-BF533 Interrupts-Each transmit and receive port generates an DMA(direct memory access)-The DMa controller trans interrupt upon completing the transfer of a data-word or fers both transmit and receive data. This reduces the after transferring an entire data buffer or buffers number and frequency of interrupts required to transfer through dma data to and from memory The uaRt has two dedicated Multichannel capability -Each SPORT Supports 128 chan DMA channels. one for transmit and one for receive. These nels out of a 1, 024-channel window and is compatible with DMa channels have lower default priority than most dma the h.100 h110. mvip-g0 and mvip standards channels because of their relatively low service rates An additional 250 mv of SPOrt input hysteresis can be The baud rate, serial data format, error code generation and sta enabled by setting bit 15 of the Pll ctl register. When this bit tus, and interrupts for the uart port are programmable is set, all SPORT input pins have the increased hysteresis The UarT programmable features include SERIAL PERIPHERAL INTERFACE(SPD PORT Supporting bit rates ranging from(fscL/1,048,576)bits per second to(fcLK/16)bits per second The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have an SPI-compatible port that enables the processor to communi- Supporting data formats from seven bits to 12 bits per frame cate with multiple SPI-compatible devices The SPI interface uses three pins for transferring data: two data Both transmit and receive operations can be configured to pins(master output-slave input, MOSI, and master input-slave generate maskable interrupts to the processor output, MISO)and a clock pin(serial clock, SCK). An SPI chip The UARt'port's clock rate is calculated as select input pin( SPISS) lets other SPi devices select the proces sor,and seven SPI chip select output pins(SPISEL7-1)let the UART CLock rate 16X UART Divisor processor select other SPi devices. The SPi select pins are recon igured general-purpose I/O pins. USing these pins, the SPi port where the 16-bit uart Divisor comes from the Uart Dlh provides a full-duplex, synchronous serial interface which sup register (most significant 8 bits)and UART_ DLL register (least ports both master/slave modes and multimaster environments significant 8 bits) The baud rate and clock phase/polarities for the SPi port are In conjunction with the general-purpose timer functions, programmable, and it has an integrated dma controller, con autobaud detection is supported figurable to support transmit or receive data streams. The SPT The capabilities of the UART are further extended with support DMa controller can only service unidirectional accesses at any for the Infrared Data Association(IrDA ) serial infrared physi- given time. cal layer link specification(SIR) protocol The SPi port clock rate is calculated as GENERAL-PURPOSE I/O PORT F SPI Clock rate CLK The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have 2×SPⅠBAUD 16 bidirectional, general-purpose 1/0 pins on Port F(PF15-0 Each general-purpose I/O pin can be individually controlled by where the 16-bit SPI- BAUD register contains a value of2 to manipulation of the GPIO control, status and interrup 65535 registers During transfers, the SPi port simultaneously transmits and GPIO direction control register- Specifies the direction of receives by serially shifting data in and out on its two serial data each individual PFx pin as input or output lines. The serial clock line synchronizes the shifting and sam the two serial data lines GPIO control and status registers- The processor employs pling of data o a write one to modify " mechanism that allows any combi UART PORT nation of individual GPiO pins to be modified in a single instruction, without affecting the level of any other GPIO The ADsP-BF531/ADSP-BF532/ADSP-BF533 processors pro pins. Four control registers are provided. One register is vide a full-duplex universal asynchronous receiver/transmitter written in order to set GPio pin values one register is writ- (UART) port, which is fully compatible with PC-standard ten in order to clear gPio pin values, one register is written UARTs. The UART port provides a simplified UART interface in order to toggle gpio pin values, and one register is writ- to other peripherals or hosts, supporting full-duplex, DMA-sup ten in order to specify GPIO pin values. Reading the GPIo ported, asynchronous transfers of serial data. The UART po status register allows software to interrogate the sense of includes support for 5 data bits to 8 data bits, I stop bit or 2 stop the gpio pir bits, and none, even, or odd parity. The UART port supports two modes of operation GPIO interrupt mask registers- The two GPIO interrupt mask registers allow each individual PFx pin to function as PIO (programmed 1/0)-The processor sends or receives an interrupt to the processor. Similar to the two GPio data by writing or reading I/O-mapped UART registers control registers that are used to set and clear individual The data is double-buffered on both transmit and receive GPIO GPIO interrupt mask regist bits to enable interrupt function, and the other GPIO inter rupt mask register clears bits to disable interrupt function Rev. F Pa

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