安森美半导体ESD保护器件EMI4182-D 数据手册pdf,安森美半导体ESD保护器件EMI4182-D 数据手册
EM|4182 TYPICAL CHARACTERISTICS 0 15 cOO 20 3-25 30 8 9 40 E 1E6 1E7 1E8 1E9 6E9 1E5 1E6 1E7 1E8 1E96E9 Frequency, Hz Frequency, Hz Figure 2. Differential Mode Attenuation VS. Fiqure 3. Common Mode Attenuation vs Frequency(diff =100 $2 Frequency(comm= 50 Q2 15 9925 oa 30 35 110 -120 1E5 1E6 1E7 1E8 1E96E9 1E五 HEr 1 1E9 B Frequency Hz Figure 4. Differential Return Loss VS Frequency Figure 5. Differential Inter-Lane Cross-Coupling zdf=100g9) A 1E6 1E0 BED Figure 6. Common Mode Inter-Lane Cross-Coupling http://onsemi.com 3 EM|4182 MIPI DSI(D-PHY MIPI DSI(D-PHY) Client EM|4182 Evaluation Board Figure 7. MIPI D-PHY LP Mode Test Setup Tek 50E:25G A歌情 500nsldiv 10.0GS/s 100pslpt 502 Stopped Single Seq CAv20Cmv RL:50.0k Cons February 28, 2011 14: 20: 20 Figure 8. EM4182 MIPI D-PHY LP Mode Measured results http://onsemi.co EM|4182 Agilent Agilent 81141A Coax cable Coax Cable DSo81204A Serial pulse data EM4182 High speed Generator Oscilloscope Test PcB Figure 9. EMI4182 Eye Diagram Test Setup File Control gotup ce ulte Hep 22M2011431 File Cortrol satp wre Analy2e Titties Hrt W/Hz Standard FA a Csak BCHE Standar 100ml 个 Horizontal scale Posit 国 trt ical scale horizontal scole Position function I 50.0 po/div Figure 10. EMI4182 Measured Eye Diagram 34Gbps(EVB through on left, EVB with EMI4182 on right http://onsemi.co EM|4182 Transmission Line Pulse(TLP)Measurements Transmission Line Pulse(tlp) provides current versus voltage (I-V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 11. TLP I-V curves of Esd protection devices accurately demonstrate the product's ESd capability because the 10 s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 12 where an & kV IEC61000-4-2 current waveform is compared with TLP current pulses at 8 and 16 AA TLP curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. Typical TLP I-V curves for the emi4182 are shown in Figure 13 SW Attenuator 50 Q2 Coax Cable 50 Q Coax Cable MMI VM 10 MQ DUT Figure 11. Simplified Schematic of a Typical TLP System 15 -IIEC 8 kV TLP SA 10 TLP 16A 5 0 120 [ns) Figure 12. Comparison Between 8 kV IEC61000-4-2 and 8 A and 16A TLP Waveforms 25 15 -15 3-10 5 0 Voltage(v Voltage v) Figure 13. Positive and Negative tLP Waveforms http://onsemi 6 EM|4182 ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an esd event to as low a voltage as possible. The Esd clamping voltage is the voltage drop across the Esd protection diode during an ESD event per the IEC61000-4-2 waveform. Since the IEC61000-4-2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all eSd protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to On Semiconductor Application Notes AND8307/D and AND8308/D IEC61000-4-2 Spec IEC61000-4-2 Waveform First Peak Voltage Current Current at Current at 100% Level (k) 30ns(A)|60ns(A) 90% 2 7.5 4 2 4 15 8 4 l@30 3 6 225 12 6 4 8 30 16 8 @ 10% tp-0. ns to 1 ns ESD Gun TVS Oscilloscope 日已日○ 50 Cable 50g ○○ Figure 14 Diagram of ESD Test Setup 100 PEAK VALUE RSM@ 8 us 90 H80 PULSE WIDTH (tP)IS DEFINED THAT POINT WHERE THE 70 PEAK CURRENT DECAY=8 us 60 HALF VALUE IRSM/2 20 us 40 0 30 。9 10 0 20 80 t, TIME (u Figure 15.8 x 20 us Pulse Waveforn http://onsemi EM|4182 35 000 15000 200.00 Time(ns) Figure 16. ESD Clamping Voltage +8 kv per IEC6100-4-2 (external to internal pin) 10 0 -10 -15 -20 40 50 150 200 Time ns Figure 17. ESD Clamping Voltage -8 kv per lEC6100-4-2 (external to internal pin) http://onsemi.co EM|4182 HDMI Type A Connecto EM|4182 TMDS Data 2+ TMDS Data 2 TMDS Data 1+ TMDS Data 1 EM|4182 TMDS Data o+ TMDS DataO- TMDS Clock+ TMDS Clock CEC SCL HEC DATA SDA lot Plug Detect NUP4114 +5VPower GND Black Top laye Red= other layer Figure 18. EMI4182 HDMI Type-A Connector Application Diagram HDMI Type D EM|4182 TMDS Data 2+ Connector TMDS Data 2 PIN 1 TMDS Data 1 TMDS Data 1 TMDS Data o+ TMDS Data TMDS Clock TMDS Clock Black Top layer Red other layer EM|4182 CEC +5V P SDA NUP4114 Figure 19. EMI4182 HDMI Type-D Connector Application Diagram http://onsemi 9 EM|4182 PACKAGE DIMENSIONS WDFN10 25X2.0.5P CASE 511 BM-01 ISSUE O L NOTES 1. D MENSIONING AND TOLERANCING PEI ASME Y145M. 1994 x010c 2. CONTROLLING DIMENSION: MILLIMETERS 3. D MENSIONS b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN PIN 1 DETAIL A COPLANARITY APPLIES TO THE EXPOSED REFERENCE ALTERNATE TERMINAL PAD AS WELL AS THE TERMINALS CONSTRUCTIONS MILLIMETERS A3 DIMMINMAX 2x00c TOP VIEW EXPOSED Cu MOLD CMPD A0700801 0.20 REF ∥0051c DETAIL B 0.15 A1 2.50 BSC 00BSC A DETAIL B 0.50 BSC ⌒0.05C ALTERNAT CONSTRUCT L1005c15 NOTE 4 SIDE VIEW A1 EATING PLANE DETAILA RECOMMENDED MOUNTING FOOTPRINT PACKAGE 030 1.07 OUTLINE 0.10 MIN 2.30 b 0.10 BOTTOM VIEW 0.05 CNOTE 3 0.45 0.50 PITCH DIMENSIONS: MILLIMETERS For additional information on our Pb-Free strategy and soldering details, please download the on Semiconductor Soldering and Mounting Techniques Reference Manual. SOLDERRM/D ON Semiconductor and (n aro registered trademarks of Semiconductor Compononts Industries, LLC (SCILLC). SCILLC reserves the right to make changos without further notico Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Al operating parameters, including "Typicals" must be validated for each customer applicatian by customer's technical experts. SCILLC does not convey any license under its patent ngts nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant in o the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLc oroduct could create a situation where personal injury or death may occur. Should Buyer purchase or use SCiLLC products for any such unintended or unauthorized application, Buyer shall indemnify anc hold Scillc and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N.AmericanTechnicalSupport800-282-9855TollFreeOnSemiconductorWebsitewww.onseml.com Literature Distribution Center for oN Semiconductor USA/Canada PO. Box 5163. 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