铁电内存的超高频RFID MB97R8030.pdf

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铁电内存的超高频RFID MB97R8030pdf,铁电内存的超高频RFID MB97R8030
PRELIMINARY MB97R8030 ■ RF INTERFACE RF signal interface is compliant with EPCglobal C1G2 Ver 1.2.0(as described in 6.3. 1) ■ SERIAL INTERFACE This LSI has SPI(Serial Peripheral Interface)interface. It is able to access FRAM User memory through the SPl interface. In this case, the external power supply is required Pin Function Description The serial Pin and its function descriptions are shown in the table below · Pin function Pin No. Pin name Function description RF interface status This is an output pin to monitor RF interface status. When BUsY is"H,, the LsI is BUSY in RF communication mode, in this case, the external power and Serial communi cation is prohibited. When BUSY is "L, the external power and sPl communication is allowed SPI Mode switch SPI This is an input pin to control to switch to Serial communication mode. When SPl is"H the lsi can be transfer to serial communication mode Chip Select This is an input pin to select chip. When XCS is"H", device is deselect (standby XCs status)as long as the LSI is not write status internally. And So becomes High-Z In this case, inputs from other pins are ignored When Xcs is ",, the lsi is seled (active status, ) XCS has to be"L" before executing op-code Write protect 10 XWP This is an output pin to protect FRAM from writing. When WXP is "L"S, FRAM mem ory is protected Serial Clock 8 SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge. so is output synchronously to a falling edge Serial Data Input This is an input pin of serial data. It inputs op-code, address, and writing data Serial Data Output so This is an output pin of serial data Reading data of FRAM memory are output Its High-Z during standby VDD Supply Voltage: 3.3 V(=0.3 v) VSs Ground FUITSU MB97R8030 PRELIMINARY 2. Connection to spl Interface This LsI works as a slave of SPl. It can be connected to the microcontroller equipped with sPl port as shown in the figure below must be disconnected and the other signal must be"L", When BUSY signal is "H". the external power The external SPl controller shall monitor the BUsY signal VDD SPI SPI XCS中 XCS XWP中 XWP SCK SCK MOSI MISO BUSY BUSY VSS VSS MB97R8030 Controller(EXternal SPI access circuit 3. SPI Mode MB97R8030 is corresponding to the SPI mode(CPOL =0, CPHA=0), and sPl mode 3 XCS SCK MSB LSB SPI mode o XCS SCK 3 MSB LSB FUITSU PRELIMINARY MB97R8030 4. Transfer procedure to Serial communication mode This LsI has BUsY signal and SPl signal to avoid the collision between RF communication mode and Serial communication mode Before transfer to the Serial communication mode, the controller must confirm the BUsY signal. If the BUsY is"H the lSi is in rF communication mode. In this case the vdd must be disconnected and the serial communication mode is prohibited. If BUSY is"L, the VDd can be connected and Serial communication is allowed The transfer procedure to Serial communication is shown in the figure below When VDd is connected, the external power 3. 3 V(+0. 3 V) is supplied. Simultaneously SPl and XCS shall be“H After the power on reset, the Serial communication is established To terminate the serial communication mode the vdd must be disconnected and spl xcs must set to be"L RF Standby communication Standby Serial communication Standby BUSY VDD (disconnection) (set to"L") XCS (set to"L") SCK/SI/SO (set to L") (Details refer COMMAND 3. Command of Serial communication mode”) FUITSU MB97R8030 PRELIMINARY 5. Power ON/OFF Sequence While transfer to Serial communication mode, the power ON/OFF sequence is shown in the figure below The xcs level hold time is shown in the table below Serial communication power ON/OFF sequence tpd 3.0V 3.0V VIH(Min) VIH(Min) 1.0V 1.0V VIL(Max) VIL(Max) XCS XcS>VoD×0.8 XCS: don't care Xcs>VoD×0.8 XCS(Max)< VDD+0.5 V Notes:. Because turning the power-on from an intermediate level cause malfunction, when the power is turned on, Vdd is required to be started form o V If the device does not operate within the specified conditions of read cycle, power on/off sequence, memory data can not be guaranteed XCS level hold time at power ON/OFF Value Parameter Unit Min Max XCS level hold time at power OFF pd 60 XCS level hold time at power ON tpu 60 Power OFF time 10 ms Power supply rising time trs 0.05 200 ms FUITSU PRELIMINARY MB97R8030 ■ MEMORY 1. Memory addressing Memory addressing in RF communication mode Memory addressing in RF communication mode use EXtensible bit vectors(EBV format, which is compliant with EPCglobal C1 G2 Ver1.2.0(Annex A) Memory addressing in Serial communication mode The logical address is used for memory addressing in Serial communication mode 2. Memory Map Memory area The memory is divided into the following five areas · Five memory areas Access command Name Memory size BANK Address range RF communication SPI communication User 832wx 16b=13, 312 bit 11 000H to 33F+ RW/S/BLW/BLE R∧W TID 14W×16b=224bt10000; to ooh R/S R EPC 35W×16b=560bit 01 000Hto022H RWS/BLW侶BLE Reserved 4W×16b=64bit 00 000Hto003H R/ System 139×16b=2,224bit L/BPL Only lock and SPl error information can be read Note: Command abbreviation: R: READ. W: WRITE S: SELECT. L: Lock. BPL: Block Permalock BLW: blockWrite blE: Block Erase The User, TID, EPC, and Reserved memory areas contain the data that is defined by the epcglobal c1G2 specification (Chapter 6.3. 2.1). The memory areas are also called as "Memory bank or "Bank"in EPC standard (In this specification, the User memory area is also called as"User memory") In each memory bank, the logical address starts from zero(00H Logical addressing in EBV-8 format is used The system area stores user memory lock intormation and Area Group passwords The memory map is shown in shown in the table on next page. The system area is not disclosed). The User memory consists of 4 Area Group and 52 Areas. The Area is defined as 16 bits word'(256 bits)"of data and each Area Group contains several areas. The first 3 Area Group contain 16 areas, the last Area Group contains 4 areas In addition, the idea of "Bank"Area and"Area" shall be ignored when using the Serial communication mode FUITSU MB97R8030 PRELIMINARY · Memory map Logical Address Logical Address A rea (RF communication) Data Description Size TotalTotal (word)communication) (word)(word)(bit) bank (bit) 0000H-00FFH000-00FH0000A-000FH Area00 16 0100H-0FFH010H-01FH0010-001FH Areal 16 Areagroupoo 0200H-0EFFH020+-0EFH0020H-00EFH Area02-14208 User 11OF004-OFFFH OFOH-OFFH00FOH-OOFFH Area15 83213,312 1000H-1FFFH100H-1FFH0100H-01FFH AreaGroup01 Area00-15256 2000H-2FFFH 200H-2FFH 0200H-02FFH AreaGroup02 Area00-15256 3000H-33FFH 300H -33FH0300H-033FH AreaGroup03Area00-03 64 0000+-000F 000 03A8 StoredCRC16(PC to EPC) 00104-001FH 0014 03AH9 StoredPC(Protocol Control) 11 EPC 01 00204-020FH002H-020H03AAH-03c8H EPC 31 02104-022FH021H-022H03C9-03CAH XPC W1 XPC W2 2 0000-000F 000 03CCH KILL-Password [31: 16 1 00104-001FH 001H 03CDH KILL-Password [15: 0 Reserved 00 4 64 0020-002FH 002 03CEH ACCESS-Password [31: 16 0030+-003FH003H 03CFH ACCESS-Password [15: 0 1 TID 100000H-00DFH000H-00DH03E0H-03EDH TID 1414224 Area 03DOH-03D1H AreaGroup00 Area Group01 2 64 Lock 03D2H-03D3H AreaGroup02 AreaGroup03 2 03D4H-03D5H AreaGroup00 AreaGroup012 64 Lock 03D6H-03D7H AreaGroup02 AreaGroup03 2 SPI ERR Info 03FFH SPI ERRO INFO 16 TID This lsi has a 96 bits tid that complies with ePC c1 G2 standard. the tid consist of the 4 items shown in the following An 8 bits data of EPC whose value is always"E2"(bit89 to bit96 A 12 bits IC manufacture code whose values is always"(bit77 to bit88) Unique 60 bits serial number assigned by Fujitsu Microelectronics(bit 1 7 to bit76 RFU 16 bits(bit1 to bit 16) Among the unique 60 bits serial number assigned by Fujitsu Microelectronics, the 8 bits from bit69 to bit76 define MB97R8030 code whose value is 03H. and 52 bits from bit 1 7 to bit68 define chip information TID contiguration MSB LSB 8988 7776 6968 1716 EPC standard “03H manufacture Chip information RFU “010A unique serial number assigned by FUJITSU MICROELECTRONICS FUITSU PRELIMINARY MB97R8030 FLAGS AND RANDOM NUMBER GENERATOR The inventoried flag, selected flag, and random number generator are compliant with EPCglobal C1 G2 Ver 1.20.( Chapter6.322,6.323,632.5) TAG STATES AND SLOT COUNTER The Tag states and slot counter are compliant with EPCglobal C1G2 Ver. 1.2.0. (Chapter 6.3. 2 4) COLLISION ARBITRATION ALGORITHM The collision arbitration algorithm is compliant with EPCglobal C1G2 Ver. 1. 2.0.(Chapter 6.3.2.6, 6.3.2.7 6328,6329) FUITSU 9 MB97R8030 PRELIMINARY I COMMAND 1. Command of rf communication mode This LsI supports all mandatory commands and optional commands that defined by EPCglobal C1 G2 Ver 1.2.0.(Chapter 6.3.2.11) In addition, the Chg Area GroupPwd and ReadLock is supported as custom com mand. the commands list and codes is shown in the table below For Block Write and Block Erase command(Optional command), parts of the specifications are different form the EPC C1G2 standard as described in"Block Write(Optional command)"and"Block Erase(Optional com mand)". ChgArea Group Pwd and ReadLock command Custom command)are described in"Chg Group Pwd( Custom command)”and“ eadlock( Custom command)” Command of rf communication mode Items Command Code Query Rep 00 ACK 01 Query 1000 Query Adjust 1001 Slect 1010 Mandatory NAK 11000000 Reg RN 11000001 Read 11000010 Write 11000011 Kill 11000100 Lock 11000101 Ac ccess 11000110 BlockWrite 11000111 Optional Block erase 11001000 BlockPermalock 11001001 Chg 1110000000000100 Custom Readlock 1110000000000111 Differences from EPCglobal c1 G2 Ver. 1.2.0 When the r/ writes the entire or part of the pc or epc area of the Tag cRc-16 stored in EPc memory OOH to OFH of the Tag is disabled until an ACK command is received and a response that is not truncated (PC, EPC, CRC-16)is returned. After the completion of responding to ACK command the correct CRC-16 value calculated during responding is written to EPC memory(00H to OFH) as well. If a truncated response to the ACK command is requested before CRC-16 is enabled, the CRc-16 value in the EPC memory, which has not been enabled is returned as is 0 FUITSU

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