ADI ADSP-BF536:有嵌入式网络连接性的Blackfin处理器英文产品数据手册.pdf

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ADI ADSP-BF536:有嵌入式网络连接性的Blackfin处理器英文产品数据手册pdf,ADI ADSP-BF536:有嵌入式网络连接性的Blackfin处理器英文产品数据手册
ADSP-BF534/ADSP-BF536/ADSP-BF537 GENERAL DESCRIPTION The ADSp-BF534/ADSP-BF536/ADSP-BF537 processors are PORTABLE LOW POWER ARCHITECTURE members of the blackfin family of products, incorporating the nalog Devices, InC /Intel Micro Signal Architecture(MSA Blackfin processors provide world-class power management Blackfin processors combine a dual-MAC, state-of-the-art sig and performance. They are produced with a low power and low nal processing engine, the advantages of a clean, orthogonal voltage design methodology and feature on-chip dynamic RISC-like microprocessor instruction set, and single-instruc- power management,which is the ability to vary both the voltage tion, multiple-data(SIMD)multimedia capabilities into a singl and frequency of operation to significantly lower overall power instruction-set architecture consumption. This capability can result in a substantial reduc tion in power consumption, compared with just varying the The ADsP-BF534/ADSP-BF536/ADSP-BF537 processors are frequency of operation This allows longer battery life for completely code and pin compatible. They differ only with portable appliances respect to their performance, on-chip memory, and presence of the Ethernet Mac module. Specific performance, memory, and SYSTEM INTEGRATION feature configurations are shown in Table 1 The Blackfin processor is a highly integrated system-on-a-chip lution for the Table 1. Processor Comparison gen nected applications By combining industry-standard interfaces with a high performance signal processing core, cost-effective applications can be developed quickly, without the need for costly external components. The system peripherals include an TEEE-compliant 802.3 10/100 Ethernet MAC(ADSP-BF536 and Features ADSP-BF537 only), a CAN 2.0B controller, a TWi controller, Ethernet mac two UART ports, an spi port two serial ports (sPorts), nine CAN general-purpose 32-bit timers(eight with PWM capability real-time clock, a watchdog timer, and a parallel peripheral (PPI) SPORTS UARTs BLACKFIN PROCESSOR PERIPHERALS The aDSP-BF534/ADSP-BF536/ADSP-BF537 processors con GP Timers 8 tain a rich set of peripherals connected to the core via severa Watchdog timers high bandwidth buses, providing flexibility in system configura tion as well as excellent overall system performance(see RTC Figure 1). The processors contain dedicated network communi Parallel Peripheral Interface cation modules and high speed serial and parallel ports, an GPIOs 48 interrupt controller for flexible management of interrupts from L1 Instruction 16K bytes 16K bytes 16K bytes the on-chip peripherals or external sources, and power manage SRAM/Cache ment control functions to tailor the performance and power L1 Instruction 48K bytes 48k bytes 48K bytes characteristics of the processor and system to many application scenarios SRAM Memory 1 Data 32K bytes 32K bytes 32K bytes All of the peripherals, except for the general-purpose I/O, CAN Configuration SRAM/Cache TWI, real-time clock, and timers, are supported by a flexible L1 Data SRAM 32K bytes 32K bytes DMA structure. There are also separate memory dma channels dedicated to data transfers between the processors various L1 Scratchpad 4K bytes bytes 4K bytes memory spaces, including external SDRAM and asynchronous L3 Boot RoM 2K bytes 2K bytes 2K bytes memory. Multiple on-chip buses running at up to 133 MHz Maximum Speed grade 500 MHz400 MHz 600 MHz provide enough bandwidth to keep the processor core running Package options: long with activity on all of the on-chip and external CSP BGA 208-Ball 208-Ball 208-Ball eriphera CSP BGA 182Bal|182Ba|182-Bal The Blackfin processors include an on-chip voltage regulator in support of the processors dynamic power management capabil By integrating a rich set of industry-leading system peripherals ity. The voltage regulator provides a range of core voltage levels and memory, the blackfin processors are the platform of choice when supplied from VDDEXT. The voltage regulator can be for next-generation applications that require RiSC-like pro bypassed at the user's discretion grammability, multimedia support, and leading-edge signal processing in one integrated package Rev. G Page 3 of 68 February 2009 ADSP-BF534/ADSP-BF536/ADSP-BF537 BLACKFIN PROCESSOR CORE instructions include byte alignment and packing operations As shown in Figure 2, the Blackfin processor core contains two 16-bit and 8-bit adds with clipping, 8-bit average operations 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUS, and 8-bit subtract/absolute value/accumulate(Saa)operations Also provided are the compare /select and vector search four video alus, and a 40-bit shifter The computation units instructions process 8-,16-, or 32-bit data from the register file The compute register file contains eight 32-bit registers. When For certain instructions, two 16-bit ALU operations can be per- performing compute operations on 16-bit operand data,the formed simultaneously on register pairs(a 16-bit high half and register file operates as 16 independent 16-bit registers. All 16-bit low half of a compute register). If the second alu is used, operands for compute operations come from the multiported quad 16-bit operations are possible register file and instruction constant fields The 40-bit shifter can perform shifts and rotates, and is used to Each MAC can perform a 16-bit by 16-bit multiply in each support normalization, field extract, and field deposit Instructions cycle, accumulating the results into the 40-bit accumulators igned and unsigned formats, rounding, and saturation The program sequencer controls the flow ofinstruction execu- are supported tion,including instruction alignment and decoding For The alUs perform a traditional set of arithmetic and logical program flow control, the sequencer supports PC relative and operations on 16-bit or 32-bit data. In addition, many special indirect conditional jumps(with static branch prediction), and instructions are included to accelerate various signal processing subroutine calls. Hardware is provided to support zero-over tasks. These include bit operations such as field extract and pop- head looping. The architecture is fully interlocked, meaning that ulation count, modulo 2multiply, divide primitives, saturation the programmer need not manage the pipeline when executing instructions with data dependencies and rounding, and sign/exponent detection. The set of video -- ADDRESS ARITHMETIC UNIT B3 2 L2 B2 ML1 B1M1 DAG1 P4 LO DAGO DA1,321444 P2 P1 DA032 RAB PREG D132 ASTAT SEQUENCER R7.HIR7 L R6.H R6.L R5.H R5.L ALIGN R4.HI R4. L R3.H R3.L R2.H R2. L DECODE R1.HR1.L BARREL ROHRO.L SHIFTER LOOP BUFFER CONTROL UNIT DATA ARITHMETIC UNIT Figure 2. blackfin Processor Core Rev. G Page 4 of 68 February 2009 DSP-BF534/ADSP-BF536/ADSP-BF537 The address arithmetic unit provides two addresses for simulta The memory DMA controller provides high bandwidth data neous dual fetches from memory It contains a multiported movement capability. It can perform block transfers of code or register file consisting of four sets of 32-bit index, modify, data between the internal memory and the external length, and base registers(for circular buffering), and eight memorv spaces additional 32-bit pointer registers(for C-style indexed stack manipulation) Internal(On-Chip)Memory Blackfin processors support a modified harvard architecture in The aDSP-BF534/ADSP-BF536/ ADSP-BF537 processors have combination with a hierarchical memory structure. Level 1(L1) three blocks of on-chip memory providing high-bandwidth memories are those that typically operate at the full processor access to the core speed with little or no latency At the Ll level, the instruction The first block is the Ll instruction memory, consisting of memory holds instructions only. The two data memories hold 64k bytes SRAM, of which 16k bytes can be configured as a data, and a dedicated scratchpad data memory stores stack and four-way set-associative cache. This memory is accessed at full local variable information processor speed In addition, multiple Ll memory blocks are provided, offering The second on-chip memory block is the Ll data memory, con- configurable mix of SRAM and cache. The memory manage sisting of up to two banks of up to 32K bytes each. Each memory ment unit(MMU) provides memory protection for individual bank is configurable, offering both cache and sram functional tasks that may be operating on the core and can protect system ity. This memory block is accessed at full processor speed registers from unintended access The third memory block is a 4k byte scratchpad SRaM, which The architecture provides three modes of operation: user mode runs at the same speed as the ll memories but is only accessible supervisor mode, and emulation mode. User mode has as data SRAM, and cannot be configured as cache memory restricted access to certain system resources thus providing a protected software environment, while supervisor mode has External (off-Chip) Memory unrestricted access to the system and core resources External memory is accessed via the ebiu. this 16-bit interface The Blackfin processor instruction set has been optimized so provides a glueless connection to a bank of synchronous DRAM that 16-bit opcodes represent the most frequently used instruc (SDRAM)as well as up to four banks of asynchronous memor tions, resulting in excellent compiled code density Complex devices including flash, EPROM, ROM, SRAM, and memory DSP instructions are encoded into 32-bit opcodes, representing mapped I/0 devices fully featured multifunction instructions. Blackfin processors The PC133-compliant SDRAM controller can be programmed support a limited multi-issue capability, where a 32-bit instruc to interface to up to 512M bytes of SDRAM. A separate row can tion can be issued in parallel with two 16-bit instructions, be open for each sdram internal bank, and the SDram con llowing the programmer to use many of the core resources in a troller supports up to 4 internal SDRAM banks, improving single instruction cycle overall performance The Blackfin processor assembly language uses an algebraic syn The asynchronous memory controller can be programmed to tax for ease of coding and readability the architecture has been control up to four banks of devices with very flexible timing optimized for use in conjunction with the C/C++ compiler, parameters for a wide variety of devices. Each bank occupies a resulting in fast and efficient software implementations M byte segment regardless of the size of the devices used, so MEMORY ARCHITECTURE that these banks are only contiguous if each is fully populated with iM byte of memory The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors view memory as a single unified 4G byte address space, using 32-bit 10 Memory Space addresses. All resources, including internal memory external The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors do memory, and I/O control registers, occupy separate sections of not define a separate I/O space. All resources are mapped this common address space. The memory portions of this through the flat 32-bit address space. On-chip I/o devices have address space are arranged in a hierarchical structure to provide their control registers mapped into memory-mapped registers a good cost/performance balance of some very fast, low latency (MMRS) at addresses near the top of the 4G byte address space on-chip memory as cache or SRAM, and larger, lower cost, and These are separated into two smaller blocks, one which contains performance off-chip memory systems. (See Figure 3) the control mmrs for all core functions and the other which The on-chip Ll memory system is the highest performance contains the registers needed for setup and control of the on memory available to the blackfin processor. The off-chip mem chip peripherals outside of the core. The MMRs are accessible ory system, accessed through the external bus interface unit only in supervisor mode and appear as reserved space to on (EBIU), Provides expansion with SDRAM, flash memory, and chip peripherals SRAM, optionally accessing up to 516M bytes of physical memory. G Page 5 of 68 February 2009 ADSP-BF534/ADSP-BF536/ADSP-BF537 ADSP-BF534/ADSP-BF537 MEMORY MAP ADSP-BF536 MEMORY MAP OXFFFF FFFF OxFFFF FFFF CORE MMR REGISTERS(2M BYTES) CORE MMR REGISTERS(2M BYTES) 0xFFE00000 0XFFE00000 SYSTEM MMR REGISTERS(2M BYTES) SYSTEM MMR REGISTERS(2M BYTES) OXFFC0 0000 0XFFc00000 RESERVED RESERVED OxFFB0 1000 0XFFB01000 SCRATCHPAD SRAM(4K BYTES) SCRATCHPAD SRAM (4K BYTES) 0xFFB00000 0XFFB00000 RESERVED RESERVED OXFFA1 4000 0xFFA14000 INSTRUCTION SRAMCACHE(16K BYTES) INSTRUCTION SRAM/CACHE(16K BYTES) OXFFA1 0000 OXFFA1 0000 RESERVED RESERVED OxFFAO CO0O OXFFAO COOO INSTRUCTION BANK B SRAM(16K BYTES) INSTRUCTION BANK B SRAM(16K BYTES) OxFFA0 8000 0XFFA08000 E>。乏zE INSTRUCTION BANK A SRAM (32K BYTES) INSTRUCTION BANK A SRAM (32K BYTES) OXFFA0 0000 0XFFA00000 RESERVED RESERVED 0xFF908000 0xFF908000 DATA BANK B SRAM/CACHE (16K BYTES) DATA BANK B SRAM/CACHE(16K BYTES) 0FF904000 oxFF904000 DATA BANK B SRAM(16K BYTES) RESERVED oXFF900000 oxFF900000 RESERVED RESERVED 0xFF908000 oXFF808000 DATA BANK A SRAM/CACHE (16K BYTES) DATA BANK A SRAM/CACHE(16K BYTES) oXFF804000 oxFF804000 DATA BANK A SRAM(16K BYTES) RESERVED oxFF800000 0xFF800000 RESERVED RESERVED oXEF000800 0xEF000800 BOOT ROM(2K BYTES) BOOT ROM②2 K BYTES oxEF000000 0xEF000000 RESERVED RESERVED 0x20400000 0x20400000 ASYNC MEMORY BANK 3(1M BYTES) ASYNC MEMORY BANK 3(1M BYTES) 0X20300000 ASYNC MEMORY BANK 2(1M BYTES) ASYNC MEMORY BANK 2(1M BYTES) 0x20200000 0X20200000 ASYNC MEMORY BANK 1(1M BYTES) ASYNC MEMORY BANK 1(1M BYTES) 0x20100000 0x20100000 ASYNC MEMORY BANK O(1M BYTES) ASYNC MEMORY BANK O (1M BYTES 020000000 oX20000000 SDRAM MEMORY (16M BYTES TO 512M BYTES) SDRAM MEMORY (16M BYTES TO 512M BYTES 0x00000000 0x00000000 Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Map Booting Nonmaskable Interrupt(NMt)-The NMI event can be The blackfin processor contains a small on-chip boot kernel generated by the software watchdog timer or by the NMi which configures the appropriate peripheral for booting. If the input signal to the processor. The NMI event is frequently Blackfin processor is configured to boot from boot ROM mem used as a power-down indicator to initiate an orderly shut ory space, the processor starts executing from the on-chip boot down of the system ROM. For more information, see Booting Modes on Page 16 Exceptions-Events that occur synchronously to program flow(in other words, the exception is taken before the Event Handling instruction is allowed to complete). Conditions such as The event controller on the Blackfin processor handles all asyn data alignment violations and undefined instructions cause chronous and synchronous events to the processor. The exceptions. Blackfin processor provides event handling that supports both Interrupts- Events that occur asynchronously to program nesting and prioritization. Nesting allows multiple event service flow. They are caused by input pins, timers, and other routines to be active simultaneously Prioritization ensures that peripherals, as well as by an explicit software instruction servicing of a higher priority event takes precedence over servic g of a lower priority event. The controller provides support for Each event type has an associated register to hold the return five different types of events address and an associated return-from -event instruction When an event is triggered, the state of the processor is saved on the Emulation- An emulation event causes the processor to ervisor stack enter emulation mode, allowing command and control of the processor via the jTag interface The blackfin processor event controller consists of two stages the core event controller(CEC)and the system interrupt con Reset-This event resets the processor troller (sic). The core event controller works with the system interrupt controller to prioritize and control all system events Rev.G Page 6 of 68 February 2009 DSP-BF534/ADSP-BF536/ADSP-BF537 Conceptually, interrupts from the peripherals enter into the Table 3. System Interrupt Controller(SIC) SIC, and are then routed directly into the general-purpose inter ruts of the cec Default Peripheral Peripheral Interrupt event MappingInterrupt ID Core Event Controller(cEc PLL Wakeup IVG The CeC supports nine general-purpose interrupts(IVG15-7 DMA Error( Generic ⅣVG7 in addition to the dedicated interrupt and exception events of DMARO Block Interrupt IVG7 these general-purpose interrupts, the two lowest priority terrupts(IvG15-14)are recommended to be reserved for DMAR1 Block Interrupt IVG software interrupt handlers, leaving seven prioritized interrupt DMARO OVerflow error IVG inputs to support the peripherals of the blackfin processor DMAR1 Overflow error IVG T'able 2 describes the inputs to the CeC, identifies their names CAN Error IVG in the event vector table(EVt), and lists their priorities Ethernet Error(ADSP-BF536 and IVGT ADSP-BF537 only) Table 2. Core Event Controller(CEC) SPORT O Error VG7 Priority SPORT T Error IVG (o ls Highest) Event Class EVT Entry PPI Error IVG 0 Emulation/Test Control SPI Error IVGZ Reset RST UARTO Error IVG7 Nonmaskable Interrupt UART1 Error IVG Real- Time Clock IG8 Reserved DMA Channel o (PPl) IVG8 Hardware error DMA Channel 3 (SPORT O Rx) IVG 56789 Core timer ⅣTMR DMA Channe4( SPORT0T× IVG9 al-Purpose Interrupt 7 IVG7 DMA Channel 5(SPOrT 1 Rx) ∨G9 General-Purpose Interrupt 8 ⅣVG8 DMA Channel 6 (SPORT 1 Tx) IVG9 6789 General-Purpose Interrupt 9 IVG9 TWI IVG10 10 General-Purpose Interrupt 10 IVG10 DMA Channel 7(SPl) IVG10 General-Purpose Interrupt 11 IVG11 DMA Channel(UARTO Rx) IVG10 General-Purpose Interrupt 12 IVG12 DMA Channel 9 (UARTO T IVG10 13 General-Purpose Interrupt 13 IVG13 DMA Channel 10 (UART1 Rx) ⅣVG10 14 General-Purpose Interrupt 14 IVG14 DMA Channel 11 (UART1 Tx ⅣVG10 14 15 General-Purpose Interrupt 15 IVg15 CAN RX IVG11 15 CAN TX IG11 System Interrupt Controller (SIc) DMA Channel 1(Ethernet Rx IVG11 17 The system interrupt controller provides the mapping and rout ADSP-BF536 and ADSP-BF537 only ing of events from the many peripheral interrupt sources to the Port H Interrupt a IVG11 prioritized general-purpose interrupt inputs of the CEC DMA Channel 2(Ethernet Tx IVG11 18 Although the processor provides a default mapping, the user ADSP-BF536 and ADSP-BF537 only can alter the mappings and priorities of interrupt events by writ ing the appropriate values into the interrupt assignment Port H Interrupt B VG11 registers (IAR). Table 3 describes the inputs into the SiC and the Timer o IG12 default mappings into the CeC Timer 1 IVG12 Event Control Timer 2 IG12 21 Timer 3 IG12 The black pI flexible mechanism t( Timer 4 IVG12 23 control the processing of events. In the CeC, three registers are d to coordinate and control events. Each register is G12 24 16 bits wid Timer 6 IVG12 CEC interrupt latch register(ILAT)-Indicates when Timer 7 VG12 26 events have been latched. The appropriate bit is set when Port f g interrupt a ⅣVG12 27 the processor has latched the event and cleared when the Port g Interrupt B ⅣVG12 I February 2009 ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 3. System Interrupt Controller(SIC)(Continued) event already detected on this interrupt input. The Ipend reg- ister contents are monitored by the sic as the interrupt Default Peripheral acknowledgement Peripheral interrupt Event Mapping Interrupt ID DMA Channels 12 and 13 NVG13 The appropriate ILat register bit is set when an interrupt rising 29 edge is detected (detection requires two core clock cycles ). The (Memory dMA Stream O) bit is cleared when the respective IPEND register bit is set. The DMA Channels 14 and 15 IG13 30 ipend bit indicates that the event has entered into the proces (Memory DMA Stream 1) sor pipeline. At this point the CEC recognizes and queues the Software Watchdog Timer IVG13 31 next rising edge event on the corresponding event input Port INterrupt B IVG13 31 minimum latency from the rising edge transition of the gener purpose interrupt to the ipend output asserted is three core event has been accepted into the system. This register is clock cycles; however, the latency can be much higher, depend updated automatically by the controller, but it can be writ- ing on the activity within and the state of the processor ten only when its corresponding IMASK bit is cleared DMA CONTROLLERS CEC interrupt mask register (IMASK)-Controls the masking and unmasking of individual events when a bit is The Blackfin processors have multiple, independent DMa set in the IMASK register, that event is unmasked and i hannels that support automated data transfers with minimal processed by the cec when asserted. a cleared bit in the overhead for the processor core. DMA transfers can occur IMASK register masks the event, preventing the processor between the processors internal memories and any of its DMA from servicing the event even though the event may be capable peripherals. Additionally, DMa transfers can be ac latched in the ILat register. This register can be read or plished between any of the DMA-capable peripherals anycom- written while in supervisor mode. (Note that general-pur external devices connected to the external memory interfaces pose interrupts can be globally enabled and disabled with including the SDRAM controller and the asynchronous mem the sTI and Cli instructions, respectively. ory controller DMA-capable peripherals include the ethernet MAC(ADSP-BF536 and ADSP-BF537 only), SPORTS, SPI port, CEC interrupt pending register(spend)- the ipenD UARTS, and PPI. Each individual DMA-capable peripheral has register keeps track of all nested events. A set bit in the at least one dedicated dma channel IPEND register indicates the event is currently active or nested at some level. This register is updated automatically The DMA controller supports both one-dimensional(1-D)and by the controller but can be read while in supervisor mode two-dimensional(2-D)DMA transfers. DMA transfer initial ization can be implemented from registers or from sets of The SIC allows further control of event processing by providing parameters called descriptor blocks three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt The 2-D DMA capability supports arbitrary row and column events shown in Table 3 on Page 7 sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to + 32K elements. Furthermore, the SIC interrupt mask register(SIC_IMASK)-Controls the column step size can be less than the row step size, allowing masking and unmasking of each peripheral interrupt event implementation of interleaved data streams. This feature is When a bit is set in the register, that peripheral event is especially useful in video applications where data can be de unmasked and is processed by the system when asserted.A interleaved on the fly. cleared bit in the register masks the peripheral event, pre venting the processor from servicing the event Examples of DMA types supported by the DMa controller include SIC interrupt status register(STC_ISR)-As multiple peripherals can be mapped to a single event, this register A single, linear buffer that stops upon completion lows the software to determine which peripheral event a circular, auto-refreshing buffer that interrupts on each source triggered the interrupt. A set bit indicates the full or fractionally full buffer peripheral is asserting the interrupt, and a cleared bit indi 1-D or 2-D DMA using a linked list of descriptors cates the peripheral is not asserting the event 2-D DMA using an array of descriptors, specifying only the SIC interrupt wake-up enable register(SIC_IWR)-By base dma address within a common page enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the In addition to the dedicated peripheral dma channels there are core be idled when the event is generated (For more infor two memory DMa channels provided for transfers between the mation, see Dynamic Power Management on Page 13.) various memories of the processor system. This enables trans Because multiple interrupt sources can map to a single general fers of blocks of data between any of the memories-including external SDRAM, ROM, SRAM, and flash memory-with mini purpose interrupt, multiple pulse assertions can occur simulta mal processor intervention. Memory dMa transfers can be neously, before or during interrupt processing for an interrupt controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism Rev.G Page 8 of 68 February 2009 ADSP-BF534/ADSP-BF536/ADSP-BF537 The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors also have an external dma controller capability via dual external RTXI RTXO DMa request pins when used in conjunction with the external bus interface unit(EBIU). This functionality can be used when a igh speed interface is required for external FIFOs and high bandwidth communications peripherals such as USB 2.0.It allows control of the number of data transfers for memDMA can be programmed to allow memDMA to have an increased Q The number of transfers per edge is programmable. This fatu priority on the external bus relative to the core SUGGESTED COMPONENTS REAL-TIME CLOCK ECLIPTEK EC38J (THROUGH-HOLE PACKAGE EPSON MC405 12pF LOAD (SURFACE-MOUNT PACKAGE) The real-time clock(rtC)provides a robust set of digital watch C1= 22pF c2=22.F features, including current time, stopwatch, and alarm. The R1= 10MQ RTC is clocked by a 32.768 kHz crystal external to the NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1 or. The RTC peripheral has dedicated power supply pins CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 rocesso SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF. so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The rtc provides Figure 4. External Components for RTC several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on pro If configured to generate a hardware reset, the watchdog timer grammable stopwatch countdown, or interrupt at a resets both the core and the processor peripherals. After a reset, programmed alarm time software can determine if the watchdog was the source of the The 32.768 kHz input clock frequency is divided down to a 1 Hz hardware reset by interrogating a status bit in the watchdog signal by a prescaler The counter function of the timer consists timer control register of four counters a 60-second counter, a 60-minute counter, a The timer is clocked by the system clock(SCLk), at a maximum 24-hour counter, and an 32, 768-day counter frequency SCLK When enabled, the alarm function generates an interrupt when TIMERS the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is There are nine general-purpose programmable timer units in for a time of day, while the second alarm is for a day and time of the processor. Eight timers have an external pin that can be con that day figured either as a pulse-width modulator(PWM)or timer The stopwatch function counts down from a programmed output, as an input to clock the timer, or as a mechanism fo value, with one-second resolution. When the stopwatch is measuring pulse widths and periods of external events. Thes enabled and the counter underflows, an interrupt is generated timers can be synchronized to an external clock input to the sev eral other associated PF pins, to an external clock input to the Like the other peripherals, the rtc can wake up the processor PPI_CLK input pin, or to the internal SclK from sleep mode upon generation of any rto wake-up event. additionally an rto wake-up event can wake up the processor The timer units can be used in conjunction with the two UARTS from deep sleep mode, and wake up the on-chip internal voltage and the Can controller to measure the width of the pulses in regulator from the hibernate operating mode the data stream to provide a software auto -baud detect function for the respective serial channels Connect rtC pins rtXi and rtXo with external components The timers can generate interrupts to the processor core provid as shown in figure 4 ing periodic events for synchronization, either to the system WATCHDOG TIMER lock or to a count of external signals The ADsP-BF534/ADSP-BF536/ADSP-BF537 processors In addition to the eight general-purpose programmable timers, include a 32-bit timer that can be used to implement a software a ninth timer is also provided This extra timer is clocked by the watchdog function. a software watchdog can improve system internal processor clock and is typically used as a system tick availability by forcing the processor to a known state through clock for generating periodic interrupts in an operating system generation of a system reset, nonmaskable interrupt(NMI),or eneral-purpose interrupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt then enables the timer Thereafter the software must reload the counter before it counts to zero from the programmed value. This protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error Page 9 of 68 February 2009 ADSP-BF534/ADSP-BF536/ADSP-BF537 SERIAL PORTS ( SPORTs) port provides a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster The aDSP-BF534/ADSP-BF536/ADSP-BF537 processors environments incorporate two dual-channel synchronous serial ports (SPORTO and SPORTI) for serial and multiprocessor commu The SPi port's baud rate and clock phase/polarities are pro nications. The SPORTs support the following features grammable, and it has an integrated DMA controller, IS capable operation configurable to support transmit or receive data streams. The SPIs DMA controller can only service unidirectional accesses at Bidirectional operation- Each SPORT has two sets of inde any given time pendent transmit and receive pins, enabling eight channels ofis stereo audio The SPl port's clock rate is calculated as Buffered(8-deep)transmit and receive ports- Each port SclK has a data register for transferring data words to and from SPI Clock Rate 2 x SPI BAUD other processor components and shift registers for shifting data in and out of the data registers where the 16-bit SPl_ BAUD register contains a value of 2 to65,535. Clocking- Each transmit and receive port can either use an external scrial clock or generate its own, in frequencics During transfers, the SPI port simultaneously transmits and ranging from(fscK/131,070)Hz to(fsCLK/2) Hz receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sam Word length- Each SPORT Supports serial data word from 3 bits to 32 bits in length, transferred most significant pling of data on the two serial data lines bit first or least significant bit first UART PORTS Framing- Each transmit and receive port can run with or The adsp-BF534/ADSP-BF536/ADSP-BF537 processors pro without frame sync signals for each data word. frame sync vide two full-duplex universal asynchronous receiver and signals can be generated internally or externally, active high transmitter (UART) ports, which are fully compatible with PC or low, and with either of two pulse widths and early or late standard UARTs. Each UART port provides a simplified UART frame sync interface to other peripherals or hosts, supporting full-duplex, Companding in hardware Each SPORT can perform DMA-Supported, asynchronous transfers of serial data.A A-law or H-law companding according to ITU recommen UART port includes support for five to eight data bits, one or dation G711. Companding can be selected on the transmit two stop bits, and none, even, or odd parity. Each UART port and/or receive channel of the sport without additional supports two modes of operation latencies PIO (programmed I/O)-The processor sends or receives DMA operations with single-cycle overhead- Each SPORT data by writing or reading t/O mapped UART registers can automatically receive and transmit multiple buffers of The data is double-buffered on both transmit and receive memory data. The processor can link or chain sequences of DMA (direct memory access)-The DMA controller trans DMA transfers between a SPORT and memory fers both transmit and receive data. 'This reduces the Interrupts- Each transmit and receive port generates an number and frequency of interrupts required to transfer interrupt upon completing the transfer of a data word or data to and from memory. The UART has two dedicated after transferring an entire data buffer, or buffers, DMA channels, one for transmit and one for receive. These through DMA DMA channels have lower default priority than most DMA Multichannel capability- Each SPORT supports 128 chan channels because of their relatively low service rates nels out of a 1024-channel window and is compatible with Each UART ports baud rate, serial data format, error code gen the H 100 H 110. Mvip-90 and mvip standards eration and status, and interrupts are programmable SERIAL PERIPHERAL INTERFACE(SPD) PORT Supporting bit rates ranging from(fcLK/1,048, 576)to (SclK/16) bits per second The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors have an SPI-compatible port that enables the processor to communi- Supporting data formats from 7 bits to 12 bits per frame cate with multiple SPI-compatible devices Both transmit and receive operations can be configured to The SPI interface uses three pins for transferring data: two data generate maskable interrupts to the processor pins(Master Output-Slave Input, MOSI, and Master Input- The UART port's clock rate is calculated as Slave Output, MISO)and a clock pin(serial clock, SCK). An SPI It pin(SPsS) lets other Spi de lect the processor, and seven SPI chip select output pins(SPISEL7-1)let UART Clock Rate 16X UARTx_ Divisor the processor select other SPI devices. The SPi select pins are reconfigured programmable flag pins. Using these pins, the SPI where the 16-bit UARTx Divisor comes from the UaRtx Dlh register(most significant 8 bits)and UARTX_DLL register(least ificant 8 bits I Page 10 of 68 February 2009

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