安森美半导体ESD保护器件CM2020-00TR-D 数据手册.pdf

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安森美半导体ESD保护器件CM2020-00TR-D 数据手册pdf,安森美半导体ESD保护器件CM2020-00TR-D 数据手册
CM202000TR Pin Descriptions PIN DESCRIPTIONS PINS NAME ESD Level DESCRIPTION 4,35 TMDS D2+ TMDS O 9pF ESD protection 6,33 TMDS D2 Va TMDS O.pF ESD protection' 7,32 TMDS D1+ 8kV TMDS 0.gpF ESD protection 9,30 TMDS D1- 8kV TMDS 0.9pF ESD protection 10,29 TMDS DO+ 8kV TMDS 0.9pF ESD protection 12.27 TMDS DO 8kV TMDS 0. gpF ESD protection 13,26 TMDS CK+ TMDS 0. 9pF ESD protection 15,24 TMDS CK 8kV TMDS 0.9pF ESD protection 16 CE REMOTE IN 2kV LV SUPPLY referenced logic level into ASIC 23 CE REMOTE OUT 8kV 5V SUPPLY referenced logic level out plus 3. 5pF ESd to connector DDC CLK 2KV LV SUPPLY referenced logic level into ASIC DDC CLK OUT 8kV 5v SUPPLY referenced logic level out plus 3.5pF ESD to connector 18 DDC DAT N 2kV LV SUPPLY referenced logic level into ASIC 21 DDC DAT OUT 8KV 5V SUPPLY referenced logic level out plus 3. 5pF ESD to connector 19 HOTPLUG DET IN 2KV LV SUPPLY referenced logic level into ASIC 20 HOTPLUG DET OUT 8kV 5V SUPPLY referenced logic level out plus 3. 5pF ESD to connector L∨ SUPPLY Bias for ce/ddC/ HOTPLUG level shifters 5V SUPPLY 2KV Current source for 5V OUt 5∨OUT 55mA minimum overcurrent protected 5v output. This output must be bypassed with a 0. 1uF ceramic capacitor 37 ESD BYP 2KV This pin must be connected to a 0. 1uF ceramic capacitor. GND N/A Supply GND reference 5,34,8,31, TMDS GND N/A TMDS ESD and Parasitic GND return 11,28,14 Note 1: These 2 pins need to be connected together in-line on the PCB Note 2: This output can be connected to an external 0. 1 uF ceramic capacitor, resulting in an increased ESd withstand voltage rating Note 3: Standard IEC 61000-4-2, CDIscHARG-=150pF, RDIscHARG:=33022, 5V_SUPPLY and LV_SUPPLY Within recommended operating conditions, GND=0V and ESD_BYP(pin 37), 5V_oUT(pin 38), and HOTPLUG DET_OUT(pin 20)each bypassed with a0 1 uF ceramic capacitor connected to GND Note 4: Human Body Model per MIL-STD-883, Method 3015, CDIscHARG:=100pF, RDscHARGe=1.5kQ2, 5V_SUPPLYand LV_SUPPLY within recommended operating conditions, GND=0v and ESD_BYP(pin 37), 5V_oUt(pin 38), and HOTPLUG DET_OUT (pin 20)each bypassed with a 0. 1uF ceramic capacitor connected to GND Note 5: These pins should be routed directly to the associated gnd pins on the hdmi connector with single point ground vias at the connector Rev.4paGe3of13www.onsemi.com CM202000TR Ordering Information PART NUMBERING INFORMATION Pins Package Ordering part Number Part Marking 38 TSSOP-38 CM2020-00TR CM2020-00TR Note 1: Parts are shipped in Tape and Reel form unless otherwise specified Backdrive protection Below, two scenarios are discussed to illustrate what can happen when a powered device is connected to an unpowered device via a HDMI interface, substantiating the need for backdrive protection on this type of interface. In the first example a dvd player is connected to a tv via an HDMi interface. If the dvd player is switched off and the TV is left on, there is a possibility of reverse current flow back into the main power supply rail of the DVD player Typically, the DVD's power supply has some form of bulk supply capacitance associated with it Because all CMOS logic exhibits a very high impedance on the power rail node when" off ", if there may be very little parasitic shunt resistance, and even with as little as a few millamps of backdrive"current flowing into the power rail, it is possible over time to charge that bulk supply capacitance to some intermediate level. If this level rises above the power-on- reset(POR)voltage level of some of the integrated circuits in the dvd player, these devices may not reset properly when the dVD player is turned back on In a more serious scenario, if any soc devices are incorporated in the design which have built-in level shifter and DRC diodes for ESD protection, there is even a risk for permanent damage. In this case, if there is a pullup resistor (such as with dDC)on the other end of the cable, then that resistance will pull the soc chips"output"up to a high level. This will forward bias the upper ESD diode in the DRC and charge the bulk capacitance in a similar fashion as described in the first example. If this current flow is high enough, even as little as a few milliamps, it could destroy one of the soc chip's internal DRC diodes, as they are not designed for passing dc To avoid either of these situations, the CM2020-00TR was designed to block backdrive current, guaranteeing no more than 5mA on any 0 pin when the lo pin voltage is greater than the CM2020-00TR supply voltage L'器UFPL丫 =OFF LV UPPLY LOW VOLTAGE ASIC LO. VOLTAGE HDMI ASIC HDMI ASIC HDM怎 OURCE HOM SINK HDNI3OURCI HDVI Figure 1. Backdrive Protection Diagram Rev.4paGe4of13www.onsemi.com CM202000TR Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS CC5V CLV 6.0 DC Voltage at any channel input 6.0 v√ Storage Temperature Range 65to+150 STANDARD (RECOMMENDED)OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP MAX UNITS 5V_ SUPPLY Operating Supply Voltage GND 55 LV_SUPPLY Bias Supply Voltage 3.3 5.5 VV Operating Temperature Range 40 85 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Supply Current 5V SUPPLY=5.0V 110 130 A Bias Supply Current LV SUPPLY=3.3V 5 A VoROP 5V_OUT Overcurrent Output 5V SUPPLY= 5.0V 100 mv Drop 55mA so 5V_OUT Short Circuit Current 5V_SUPPLY= 5.0V, 135175 mA Limit 5V OUT= GND OFF state leakage current, level LV SUPPLY OV 0.1 A shifting nfet BACKDRIVE Current conducted from output 5V_SUPPLY Vc 0.1 5 A pins to V_SUPPLY rails when Signal pins: TMDS_D[2: 0]+/-, powered down TMDS CK+/- CE REMOTE OUT DDC DAT OUT, DDC CLK OUT HOTPLUG DET OUT. 5V OUT Only BACKDHIV, CEC Current throug CE-REMOTE IN= LV SUPPLY< 0.1 A CE-REMOTE OUT When CE REMOTE OUT powered down Rev.4paGe5of13www.onsemi.com CM202000TR SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE drop across level LV SUPPLY=25V,V。=GND 75 95 140mV shifting NFet when ON 3mA Diode Forward Voltage l=8mA,T=25 Top Diode 0.60.85095 Bottom Diode 0.60.85095 ESD Withstand Voltage, contact Pins 4, 7, 10, 13, 20,21,22, 23, 24,+8 KV discharge per IEC 61000-4-2, 30, 33, 38:T=25C standard(IEC) Note 2 Channel clamp voltage T8=25℃,|=1A,t=8/20uS: Positive T ransients Note 3 Negative Transients 10.8 2.1 R Dynamic Resistance DYN =1A.t=8/20μS,T=25℃ Positive transients Note 3 14 Negative Transients 0.9 LEAK TMDS Channel Leakage Current 5°C 0.01 UA CIN TMDS TMDS Channel Input 5V SUPPLY= 5. 0V Measured at 0.9 1.2 pF Capacitance 1MHZ.V=25V △ C, TMDS TMDS Channel Input 5V SUPPLY= 5. 0V Measured at 0.05 F Capacitance Matching 1MHz. V=2.5V Note 4 CIN DDC Level Shifting Input Capacitance,I 5V_SUPPLY= 5.0V, Measured at 3.5 4 pF Capacitance to gnd 100KHz, Va=2.5V; Note 2 C CEC Level Shifting Input Capacitance, 5V_SUPPLY=5.0V 3.5 pF Capacitance to gND Measured at 100KHz V-2.5V C HP Level Shifting Input Capacitance, I 5V_SUPPLY= 5.0V, Measured at 3.5 Capacitance to gNd 100KHZ, VIAs=2.5V Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified Note2: Standard IEC 61000-4-2, CDIscHARGe=150pF, RoISCHARGE-330S2, 5V_ SUPPLY and LV_ SUPPLY within recommended operating conditions, GND=OV and ESD_BYP(pin 37), 5V_OUT (pin 38 ), and HOTPLUG_DET_OUT (pin 20)each bypassed with a 0. 1 uF ceramic capacitor connected to GND Note 3: These measurements performed with no external capacitor on ESD_ BYP Note 4: Intra-pair matching, each TMDS pair(i.e. D+, D- Rev.4paGe6of13www.onsemi.com CM202000TR Performance Information Typical Filter Performance (T=25C, DC Bias=oV, 50 Ohm Environment) CH1 1曰gMAG dB/REFd目 - oOb M 4-19 -6 10 10 100 1000 6000 Frequency(MHz) Figure 2, Insertion LOss VS Frequency(TMDs_D1-to GND) Rev.4paGe7of13www.onsemi.com CM202000TR Application Information SV SUPPLY 5 OUT CM2020-00TR V SUPPLY ■I■ 5■ ■■■ TMDS D TMDS GND THOS 9■■ TMDS D2. TMDS D1+ TME D1- TMDS GND TNOS 31口 ■■ NOTE 1 30■■ TMDS_D1 29■ TMDS DO 28 ■■■ TMDS DO- ■■■ TMDS CK ■■■ TMDS GND TMDS CK ASK CEc ■■ CE REMOTE NOTE 2 NIC ASIC E DDC CUK DDC DAT NOTE 4 NoTE3○GD +5V OUT ■■ HOTPLUG D Ec HDMI Connector CEC VcEC 27k? Fo当 Rsa d RpD CHp COUT akn 2k 2 15k 1COnF 1CCnF LAYQIIT NOTES NOTE 1)Differential TMDS Pairs chould be designed as normal 1002 HDMI microtrip Sinde Ended TMDs tracee undemeath CM2020 and between CMe020 and Connector ehould be tuned te match chip/connecter parasitics. (See Mdia Guard Applicatin Noles) NOTE 2)Level shiter aignal thoul be biased witha weak pullup to the desired local LV SUPPLY, H the leal ASIC includee euHisiert ups to register a logc high when the CM2020 ET iotf. then etemal pullups are nct needed NoTE 3)Place CM2020 as clee to enactor as possble and as with amy comtrolled mpedance Ina avoid ANY silkscreening wer TIMDS lines NOTE 4)CEC pullup isolation. The 27k Rcec and a Schottky DcEcprovicle the necessary slaton kr the CEC pullup. Figure 3. Typical Application for CM2020-00TR Rev.4paGe8of13www.onsemi.com CM202000TR Application Information(cont'd) Design Considerations ESD Bypass Pin 37(ESD_ BYP)is provided for an optional external ESd bypass capacitor only (i.e. 0. 1 mF ceramic. )It should not be connected to any supply rail 5V Overcurrent output Maximum Overcurrent Protection output drop at 55mA on 5V OUT is 100mV. To meet HDMI output requirements of 4.8-5.3V, an input of greater than 4 9v should be used(i.e. 5 1V+/-4%).AO 1 uF ceramic bypass capacitor on this output is also recommended Hotplug Detect Input To meet the requirements of HDMI CtS TID7-12, the following pullup/pulldown configuration is recommended for a 3.3V+/-10% internal VCC rail see Figure 4 below). A01uF ceramic capacitor is recommended for additional edge debounce and ESD bypass DUT On vs, dut off Many HDMI CTS tests require a power off condition on the System Under Test. Many Dual Rail Clamp(DRC) ESd diode configurations will be forward biased when their Vdd rail is lower than the l/o pin bias, thereby exhibiting extremely high apparent capacitance measurements, for example. The Media guard backdrive isolation circuitry limits this current to <5uA, and will help ensure compliance Rev.4paGe9of13www.onsemi.com CM202000TR LYSUPPLY 02020 LU BrASs 3 O CD 12 Ot 6D- D吧 16cECt CEC.2s ecEC BICCLK I- N/c 1 191PD.I HPD 1z ntc cAn LV DOMAIN 5v DOMAIN IN" TO AStC"OUT. TO CABLE Figure 4. Design Example Rev.4Page10of13www.onsemi.com

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