详解NAND Flash技术
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Chapter 5
NAND Flash Technology
M.F. Beug
Abstract This chapter describes the basic operating principle and presents the
major reliability and scaling limitations of floating gate NAND non-volatile memory
as used in SSD applications. It further discusses charge trapping memory cells as
a potential replacement for floating gate cells in the NAND array and evaluates the
potential of both memory cell principles in future 3D memory approaches.
5.1 Flash for SSD Application
Flash memory for non-volatile data storage was introduced commercially in the
mid-1980s. Since then, common ground NOR and NAND architecture have become
the most common memory array architectures. Traditionally, NOR Flash is used for
code storage due to faster memory cell access. NAND Flash is used for mass data
storage as a result of its higher memory density, enabling higher storage capacities.
The memory cell area difference can already be seen from the schematic NOR
andNANDarrayimagesinFig.5.1. In the NOR array, two memory cells each
share one contact to ground and one contact to the bit line (see Fig. 5.1a). This
results in an effective memory cell area of about 10 F² (where F is the minimum
feature size). The effective memory cell area of NAND cells is only slightly more
than4F².Figure5.1b shows the so-called NAND string with up to 64 memory cells
connected in a row. To operate the NAND string two additional select transistor
devices (GSL: “Ground Select Line” and SSL: “String Select Line”) and contacts to
ground (SL: “Source Line”) and the bit line (BL) need to be added. These additional
structures cause the effective cell area consumption to be slightly higher than 4 F²
M.F. Beug ()
Physikalisch-Technische Bundesanstalt (PTB), Division 2 “Electricity”, Bundesallee 100,
38116 Braunschweig, Germany
e-mail: Florian.Beug@ptb.de
R. Micheloni et al., Inside Solid State Drives (SSDs), Springer Series
in Advanced Microelectronics 37, DOI 10.1007/978-94-007-5146-0
5,
© Springer ScienceCBusiness Media Dordrecht 2013
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