<span xss=removed>Area and power efficiency of ADC can benefit from the threshold configurable comparator based SAR ADC architecture. This work proposes a threshold control technique for CMOS comparator design with high linearity. One pair of binary weighted pMOS capacitor arrays is used to generate the built-in threshold levels; another pair of digitally switched pMOS capacitor arrays is implemented to compensate the nonlinearity for the generated threshold levels.
