美信 ICL7106-ICL7107 AD规格书文件，官方规格书，模拟器件
ICL7106/CL7107 312 Digit A/D Converters ELECTRICAL CHARACTERISTICS (continued) Note 3) PARAMETER CONDITIONS N TYP MAX UNITS ICL7106 Only Pk-Pk Segment Drive Voltage √+to∨-=gV 4 6 Pk-Pk Backplane Drivc Voltage(Noto 5) ICL7107 Only (Except pin 19)V+= 5.0v, segment voltage 3V 8.0 mA Segment Sinking Current Pin 19 only 10 16 Note 3: Unless otherwise noted, specifications apply to both the ICl7106 and ICL7107 at TA=+25 C, fCLOCK= 48kH7 ICL7106 is tested in the circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2 Note 4: See the Differential input section Note 5: Backplane drive is in phase with segment drive for "off segment, 180 out of phase for on"segment. Frequency is 20 times the conversion rate. Average dc component is less than 50mV Maxim Integrated CcL7106/CcL7107 3/2 Digit AD Converters Guaranteed overload Recovery Time ey Parameters Guaranteed over Temperature Significantly Improved ESD Protection(Note 7) Negligible Hysteresis ◆ Low Noise Maxim Quality and Reliability Increased Maximum Rating for Input Current( Note 8) ABSOLUTE MAXIMUM RATINGS: This device conforms to the Absolute Maximum Ratings on adjacent page ELECTRICAL CHARACTERISTICS: Specifications below satisty or exceed all"tested"parameters on adjacent page (V+-9V; TA 25"C: fCLOCK 48kHz; test circuit-Figure 1: unless noted) PARAMETERS CONDITIONS MiN TYP MAX UNITS Zero Input Reading VIN=0.0v, Full Scale=200.0mV TA 25C(Note 6 000.0±0000+0000 Digital 0°≤TAs70c(Nate10 000.0 ±0U00+D00.0 Reading Ratiometric Readin VIN= VREF VE 100mV TA 25C(Note 6) 999 999/10001000 Digital 0≤TA≤70°c(Note10) 998999/10001001 eading Rollover Error( Difference in vN=+VN≈2000mv reading for equal positive and A=25°C(Note6) ±2 Counts negative reading near Full Scale 0≤TA<70°C(Note10) ±,2 Linearity(Max deviation from Full Scale 200.0mV 土 Counts best straight line fit) or full scale 2000V Common Mode Rejection Ratio ±1V,vN=0V Full Scale =s 200. 0mV 50 V/V Noise(Pk-Pk value not exceeded IN= OV 95% Of time) Full Scale 200. 0mV 15 Input Leakage Current 0 TA=25'C(Note 6) A 0°sTAs70°c 20 200 Zero Reading Drift N 0≤TAs70° C(Note6 C.2 V/°C Scale Factor Temperature VIN =199. 0mV Coefficient 0°sTA≤70°c ppm/'C (Ext Ref Oppm/C)(Note 6) Vt Supply Current N 0 (Does not include LED current A=25° 0.6 1.8 mA for 7107) 0°≤TA≤70c 2 V- Supply Current(7107 only) 0.6 18 mA Analog Common voltage(with 25kn between Common 2.4 2.8 3.2 respect to Pos Supply Pos Supply Temp. Coeff. of Analog Common 25kn between Common 75 ppm/° with respect to Pos Supply) Pos Supply 7106 Only(Note 5) V+ to v-= 9V 6 Pk-Pk Segment Drive voltage Pk-Pk Backplane Drive voltage 7107 Only-Segment Sinking Current+=5.0V 5 8.0 mA (Except Pin 19) Segment Voltage 3V (Pin 19 only) 10 16 7106 Only--Test Pin Voltage With Respect to V 5 Overload Recovery Time VIN changing from±10v 0 Measurement (Note 9) to ov Cycles Note 6: Test condition is VIN applied between pin fH-Hi and IN-LO through a 1Mn series resistor as shown in Figures 1 and 2. Note 7: All pins are designed to withstand electrostatic discharge(ESD) levels in excess of +2kV (Test circuit per Mil Std 883, Method 3015.1 Note 8: Input voltages may exceed the supply voltage provided the input current is limited to t imA (This revises Note 1 on adacent page) Note 9: Number of measurement cycles for display to give accurate reading Note 10: 1MS2 resistor is removed in Figures 1 and 2. Maxim Integrated ICL7106/CL7107 312 Digit A/D Converters 0.1 LCD D splay LEO 3 Display ANALOG ORIVE 219SEGMENT 八NLO 21 MINUS SIGN BACKPLANE N Lo AI!!5a47AF 7k50·F 3EˇRE 022F AEFNI a22,F RE时 HEEL C2 ascs os TOANAL ICL,107 cL7106 r口AAL0 00p MMON [032 FULL SCALE ULL SCALE 2000 my 1000 my 2000mV 1000mv pure 1 Maxim /CL7106 Typical Operating Circuit Figure 2. Maxim ICL 7107 Typical Operating Circuit Analog Section Zero integrator Phase Figure 3 shows the Block Diagram of the Analog Section for the ICL7136 Each measurement cycle is divided into Input low is shorted to analog CoMMON and the refer four phases ence capacitor is charged to the reference voltage. A 1.Auto·zero(Az feedback loop is closed around the system to input high, causing the integrator output to return to zero. This 2. Signal Integrate(INT) phase normally lasts between 11 and 140 clock pulses 3. Reference De-lntegrate(Dl) but is extended to 740 clock pulses after a"heavy"over- range conversion. 4. Zero Integrator(Zlj Differentia/ Reference Auto-Zero Phase Three events occur during auto-zero. The inputs, IN-HI The reference voitage can be generated anywhere within and IN-LO, are disconnected from the pins and internally the power supply voltage of the converter. The main shorted to analog common. The reference capacitor is source of common-mode error is a rollover voltage. this charged to the reference voltage. and lastly, a feedback is caused by the reference capacitor losing or gaining loop is closed around the system to charge the auto-zero charge to stray capacitance on its nodes the reference capacitor CAz to compensate for offset voltages in the capacitor can gain charge (increase voltage)if there is a comparator, buffer amplifier and integrator the inherent large common-mode voltage. This happens during de-in noise of the system determines the A-Z accuracy. tegration of a positive signal. In contrast, the reference SignalIntegrate Phase capacitor will lose charge(decrease voltage) when de-in tegrating a negative input signal. Rollover error is caused The internal input high(IN-Hl) and input low(IN-LO)are by this difference in reference for positive or negative connected to the external pins, the internal short is re- input voltages. This error can be held to less than half a moved and the auto-zero loop is opened. the converter count for the worst-case condition by selecting a refer then integrates the differential voltage between IN-HI ence capacitor that is large enough in comparison to the and IN-LO for a fixed time. This differential voltage can stray capacitance. (See component value selection. be within a wide common-mode range(within one volt of either supply). If, however, the input signal has no return Differential Input with respect to the converter power supply, IN-LO can be Differential voltages anywhere within the common- tied to analog common to establish the correct common- mode range of the input amplifer can be accepted by mode voltage. The polarity of the integrated signal is de- the input(specifically from iv below the positive termined at the end of this phase supply to 1.5V above the negative supply ). The sys Reference De-integrate tem has a CMRR of 86dB(typ)in this range. Care IN-Hl is connected across the previously charged refer be exercised, however, to ensure that th ence capacitor and N-Lo is internally connected to ana integrator output does not saturate, since the in log common. Circuitry within the chip ensures that the tegrator follows the common-mode voltage. A large capacitor will be connected with the correct polarity to positive common-mode voitage with a near full-scale cause the integrator output to return to zero. the input negative differential input voltage is a worst-case signal determines the time required for the output to re- condition. When most of the integrator output swing turn to zero. The digital reading displayed is has been used up by the positive common-mode voltage, the negative input signal drives the integra 1000×N tor more positive. The integrator swing can be re duced to less than the recommended 2V full-scale swing with no loss of accuracy in these critical Maxim Integrated CcL7106/CcL7107 3/2 Digit AD Converters RFF自uFF INTEGRATOR A VOLT 10A /CL7 1 DIGITAL ICL, SECTION p⑧ HEFFRE剂CE COMMON 189 Figure 3. Analog Section of /CL7106// 7107 Figure 4. Using an External Reference applications. The integrator output can swing within None of the above problems are encountered when us 0. 3V of either supply without loss of linearity ing an external reference. The ICL7106, with its low pow er dissipation, has none of these problems with either Analog Common an external reference or when using analog Common as a reference The primary purpose of this pin is to set the common- mode voltage for battery operation This is useful when During auto-zero and reference integrate the internal in using the ICL7106, or for any system where the input put low is connected to Analog Common. If IN-LO is dif signals are floating with respect to the power supply. A ferent from analog-common, a common-mode voltage voltage of approximately 2. 8V less than the positive sup exists in the system and is taken care of by the excellent ply is set by this pin. the analog common has some of CMRR of the converter. In some applications, however, the attributes of a reference voltage. If the total supply IN-LO will be set at a fixed known voltage (e.g,power voltage is large enough to cause the zener to regulate supply common). Whenever possible analog common >7V), the common voltage will have a low output im should be tied to the same point, thus removing the com- pedance(approximately 1552), a temperature coefficient mon-mode voltage from the converter. the same holds of typically 80ppm/C, and a low voltage coefficient true for the reference voltage. If convenient, REF-LO (.001%) should be connected to analog common. This will re- The internal heating of the ICL7107 by the LEd display tem move the common- mode voltage from the reference sys drivers degrades the stability of Analog Common.The power dissipated by the LED display drivers changes Analog Common is internally tied to an N-channel FET with the displayed count, thereby changing the tempera that can sink 30mA or more of current. this will hold the ture of the die, which in turn results in a small change in Analog Common voltage 2.8V below the positive supply the Analog Common voltage. This combination of vari- (when a source is trying to pull the common line positive able power dissipation, thermal resistance, and tempera There is only 10uA of source current, however, So COM ture coefticient causes a 25-80uV increase in noise MON may easily be tied to a more negative voltage, thus near full scale. Another effect of LED display driver pow over-riding the internal reference er dissipation can be seen at the transition between a full scale reading and an overload condition Overload is a Test low power dissipation condition since the three least sig nificant digits are blanked in overload On the other hand Two functions are performed by the test pin the first is a near full scale reading such as 1999 has many seg using this pin as the negative supply for externally gener ments turned on and is a high power dissipation condi ated segment drivers or any other annunciators the user tion. The difference in power dissipation between over. may want to include on the LCD. this pin is coupled to load and full scale may cause a ICL7107 with a negative the internally generated digital supply through a 500n temperature coefficient reference to cycle between over- resistor. This application is illustrated in Figures 5&6 oad and a near full scale display as the die alternatel A lamp test is the second function. All segments will be heats and cools. An ICL7107 with a positive Tc refer turned on and the display should read-1888, when ence will exhibit hysteresis under these conditions: once TEST is pulled high(V+) put into overload by a voltage just barely more than full scale, the voltage must be reduced by several counts Caution: In the lamp test mode, the segments have a before the IcL7107 will come out of overload constant dc voltage (no square wave). This can burn the CD if left in this mode for several minutes Maxim Integrate g ICL7106/CL7107 31 Digit A/D Converters The ICL7107 is identical to the ICL7 106 except that the backplane and drivers have been replaced by N-channel segment drivers. The ICL7107 is designed to drive com- 4049 mon anode LED's with a typical segment current of 8mA Cl7106 Pin 19(thousands digit output) sinks current from two LED segments, and has a 1 6ma drive capability. TO LCD The polarity indication is"on "for negative analog inputs, DECIMAL for both the icl7106 and ICL7107. If desired IN-Hl and IN-Lo can be reversed giving a"on"for positive analog TEST TO LCD BACKPL ANE System Timing The clocking circuitry for the ICL7106 and ICL7107 is Figure 54. Fixed Decima/ Point Drivers illustrated in Figure 7. Three approaches can be used 1. A crystal between pins 39 and 40 2. An external oscillator connected to pin 40. 3. An RC oscillator using all three pins The decade counters are driven by the clock frequency O LCD CE CIUAL PO NT divided by four. this frequency is then further divided to ICL7106 form the four convert-cycle phases, namely: signal inte I MSI grate (1000 counts), reference de- integrate (0 to 2000 counts), auto-zero(260 to 2989 counts)and zero integra 1O LCD tor(11 to 740). The signal integration should be a multiple of 60Hz to achieve a maximum rejection of 60Hz pickup. Oscillator Figure 5B. FiXed Decimal Point Drivers frequencies of 30kHz, 40kHz, 48kHZ, 60kHZ, 80kHz 120kHz, 240kHz, etc, should be selected. Similarly, for 50Hz rejection, oscillator frequencies of 200kHz, 100kHz, 662/3kHZ, 50kHz, 40kHz, etc, are appropriate Note that 40kHz(2.5 readings/second)will reject both 50 and 60Hz(also 400 and 440Hz) TO LC DECIMAL DECIMAL Autozero receives the unused portion of reference CL7106 POINT POINTS SELEC deintegrate for signals less than full-scale. A complete measurement cycle is 4,000 counts(16,000 clock puls es), independent of input voltage. As an example, an os cillator frequency of 48kHz would be used to obtain three 4030 dings per second GND Figure 6. Excusive"OR""Gate for Decima/ Point Drive Digital Section The digital section for the ICL7106 and ICL7107 is illus OUNTER trated in Figures 8 and 9 In Figure 8, an internal digital ground is generated from a 6v zener diode and a large P. channel source follower. This supply is made stiff to ab 2-3上 sorb the large capacitive currents when the back plane BP)voltage is switched. The BP frequency is calculated CRYSTAL by dividing the clock frequency by 800. For example, with EXTERNAL a clock frequency of 48KHz (3 readings per second), the OsI1LAIOH AC NETWORK 7189 backplane will be a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same TEST PIN UN ICL/1 frequency and amplitude. Note that these are out-of- SROIIND PIN ONICL2107 phase when the segment is ON and in-phase when OFF. Negligible dc voltage exists across the segments in ei ther case Figure 7, clock Circuits Maxim Integrated CcL7106/CcL7107 3/2 Digit AD Converters :H A LCD BACKPLANE LCD PHASE DRIVER I YPICAL SFGMENT OUTPUT picoT QECODE DEcoD 200 UTPUIT LATCH INTERNAL DIGITAL GROUND THOUSAND HUNDR← TENS TO SWITCH DRIVENS FROM COMPARATOR OUTPUT CLOCK LOGIC CONTROL WO TEST IN TEHNAL DIGITAL GROU o CL7 10 Figure 8. ICL7106 Digital Section 日日 LED TYPICAL SEGMENT OUTPUT 7 SEGMENT 7sEGMEN DECODE IE CODE DIGITAL GROUND THOUSAND HUNOREDS 山NIs TO SWITCH DRIVE RS FROM COMPARATOR OUTPUT CLOCK e TEST CON TROL LOGIC ITaL osc n osc 3 Figure 9./CL7107 Digital Section Maxim Integrate eg ICL7106/CL7107 32 Digit AD Converters Component Value Selection Reference Voltage An analog input voltage of VIN equal to 2(VREF) is re Auto-Zero Capacitor quired to generate full scale output of 2000 counts. Thus for 2V and 200mv scales, VREF should equal 1V and The noise of the system is influenced by the auto-zero 100mv respectively. However, there will exist a scale capacitor, For the 2V scale, a 0.047uF capacitor is ade factor other than unity between the input voltage and the quate. A capacitor size of 0.47uF is recommended for digital reading in many applications where the A/D is 200mv full scale where low noise operation is very im- connected to a transducer portant. Due to the Zl phase of Maxims ICL7106/7 noise can be reduced by using a larger auto-zero capaci As an example, the designer may like to have a full tor without causing hysteresis or overrange hangover scale reading in a weighing system when the voltage problems seen in other manufacturers'ICL7106/7 which from the transducer is 0. 682V. The designer should do not have the Zi phase use the input voltage directly and select VREF at 0. 341V instead of dividing the input down to 200mv. Suitable values of the capacitor and integrating Reference capacitor resistor would be 0.22uF and 120K n. This provides for a slightly quieter system and also avoids a divider For most applications, a 0.1uF capacitor is acceptable network on the input. The ICL7107 can accept input However, a large value is needed to prevent rollover er- signals up to±3.5 y with±5 v supplies. Another ror where a large common-mode voltage exists (i.e, th advantage of this system occurs when the digital REF-Lo pin is not at analog common) and a 200mV reading of zero is desired for VIN# zero. Examples scale is used. generally, the roll over error will be held are temperature and weighing systems with variable half a count by using a 1.OuF capacitor. tare. By connecting the voltage transducer between Integrating Capacitor VIN poSitive and common, and the variable(or fixed offset voltage between common and VIN negative To ensure that the integrator will not saturate the offset reading can be conveniently generated approximately 0. 3V from either supply), an appropri- ate integrating capacitor must be selected. A ICL7107 Power Supplies nominal +2v full-scale integrator swing is accept- The ICL7107 is designed to operate from t 5V supplies able for the ICL7 106 or ICL7 107 when the analog However, when a negative supply is not available it can common is used as a reference. a nominal +3.5 to 4 be generated from a clock output with two diodes, two volt swing is acceptable for the ICL7107 with a +5V capacitors, and an inexpensive IC. Refer to Figure 10 supply and analog common tied to supply ground Alternatively a-5V supply can be generated using Max- The nominal values for CINT is 0. 22uF for three read im's ICL7660 and two capacitors Ings per second (48kHz clock). These values should be changed in inverse proportion to maintain the A negative supply is not required in selected applications same output swing if different oscillator frequencies he conditions to use a single 5V supply are are used e An external reference is used The integrating capacitor must have low dielectric ab- The signal is less than t1.5V sorption to minimize linearity errors. Polypropylene ca. pacitors are recommended for this application The input signal can be referenced to the center of the common-mode range of the converter Integrating Resistor See Figure 18 The integrator and the buffer amplifier both have a class A output stage with 100uA of quiescent current 20uA of drive current can be supplied with negligible non-linearity This resistor should be large enough to maintain the am plifiers in the linear region over the entire input voltage range, The resistor value, however, should be low enough that undue leakage requirements are not placed N914 on the pc boards. For a 200mV scale, a 47Kn resistor is OSc 3 047uF recommended; (2V scale/470Kn) osc∥ ator components cL7107 A 100Kn2 resistor is recommended for all ranges ot tre. GND quency. By using the equation f = 0.45/RC, the capaci- tor value can be calculated. For 48kHz clock, (3 read v--33v ings/second), the oscillator capacitor plus stray capaci- tance should equal 100pF Figure 10. Generating Negatve Suppy from + 5v Maxim Integrated CcL7106/CcL7107 372 Digit AD Converters Applications Information Heat is generated within the ICL7107 IC package due to B VCC the sinking of LED display current. Fluctuating chip tem- perature can cause a display to change reading if the 9 internal voltage reference is used By reducing the power 8 being dissipated such variations can be reduced. The ICL7107 power dissipation is reduced by reducing the LED common anode voltage. The curve tracer illustration showing the relationship between the output current and the output voltage for typical ICL7107 is seen in Figure 5 11. Note that the typical ICL7107 output is 3. 2V (point A) 4 since the typical LED has 1.8V across it(8ma drive cur- rent) and its common anode is connected to +5V. Maxi- mum power dissipation is 81mA×32V×24 segments=622mW Once the iCL7107 output voltage is above 2V, the LED current is essentially constant as output voltage increas- 12|3456|7|8910 es Point B illustrates that reducing the output voltage by 0.7V results in 7.7mA of LED current, (only 5% reduc SEGMENT tion). The maximum power dissipation is a reduction of 26% as calculated by Figure /1. /CL7107 Output Cunrent vs Output Voltage 7.7mA×2.5V×24 segments=462mW As illustrated in Figure 12, reduced power dissipation is easy to obtain This can be accomplished by placing ei- ther a 5.12 resistor or a 1 amp diode in series with the display(but not in series with the ICL7107). Point C of Figure 18 illustrates that a resistor will reduce the ICL7107 output voltage when all 24 segments areOn The output voltage will increase when segments are turned"Off". On the other hand the diode will result in a relatively steady output voltage, around Point B. the re- sistor not only reduces the change in power dissipation as the display changes but also limits the maximum DIsPLa power dissipation. This is due to the fact that as fewer segments are"On", each"On"output drops more volt age and current. The resistor circuit will change about 230mw when changing from the best case of six seg /CL7107 ments, a"display, to worst-case of a1888"di play. If the resistor is removed the power dissipation change will be 470mW. The resistor, therefore, will re duce the effect of display dissipation on reference volt age drift by about 50% 恶 As more segments are turned off the change in lED LED Display brightness caused by the resistor is almost unnoticeable. A diode may be used instead of the resistor if it is impor- tant to maintain a steady level of display brightness Figure 12 Diode or Resistor Limits Package Power Dissipation 10 Maxim Integrated