UM10211
LPC2364/6/8/78 User manual
Rev. 01 — 6 October 2006 User manual
Document information
Info Content
Keywords LPC2300, LPC2364, LPC2366, LPC2368, LPC2378, ARM, ARM7, 32-bit,
USB, Ethernet, CAN, I2S, Microcontroller
Abstract An initial LPC2364/6/8/78 User manual revision
UM10211_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 6 October 2006 2 of 612
Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com
Philips Semiconductors
UM10211
LPC23xx User manual
Revision history
Rev Date Description
01 20061006 Changes made to 20061002 edition:
• Pad structure details added in Table 8–79 “LPC2364/6/8 pin description” and Table
8–80 “LPC2378 pin description”
• order of the “On-Chip RAM“ elements adjusted in Table 2–3 “LPC2300 memory usage”
20061002 Preliminary LPC234/6/8/78 User manual
UM10211_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 6 October 2006 3 of 612
1. Introduction
LPC2364/6/8/78 is an ARM-based microcontroller for applications requiring serial
communications for a variety of purposes. These microcontrollers incorporate a 10/100
Ethernet MAC, USB 2.0 Full Speed interface, four UARTs, two CAN channels, an SPI
interface, two Synchronous Serial Ports (SSP), three I
2
C interfaces, an I2S interface, and
a MiniBus (LPC2378 only: 8-bit data/16-bit address parallel bus).
Important: Term “LPC2300“ in the following text will be used as a generic name for all
four parts covered with this user manual: LPC2364, LPC2366, LPC2368, and LPC2378.
Only when needed, a specific device name will be used to single out one of them.
2. Features
• ARM7TDMI-S processor, running at up to 72 MHz.
• Up to 512 kB on-chip Flash Program Memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Single Flash sector or full chip erase in
400 ms and 256 bytes programming in 1 ms. Flash program memory is on the ARM
local bus for high performance CPU access.
• Up to 32 kB of SRAM on the ARM local bus for high performance CPU access.
• 16 kB Static RAM for Ethernet interface. Can also be used as general purpose SRAM.
• 8 kB Static RAM for USB interface. Can also be used as general purpose SRAM.
• Dual AHB system that provides for simultaneous Ethernet DMA, USB DMA, and
program execution from on-chip Flash with no contention between those functions. A
bus bridge allows the Ethernet DMA to access the other AHB subsystem.
• External memory controller that supports static devices such as Flash and SRAM. An
8-bit data/16-bit address parallel bus is available in LPC2378 only.
• Advanced Vectored Interrupt Controller, supporting up to 32 vectored interrupts.
• General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial
interfaces, the I2S port, and the SD/MMC card port, as well as for memory-to-memory
transfers.
• Serial Interfaces:
– Ethernet MAC with associated DMA controller. These functions reside on an
independent AHB bus.
– USB 2.0 Device with on-chip PHY and associated DMA controller.
– Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO. These reside on the APB bus.
– Two CAN channels with Acceptance Filter/FullCAN mode reside on the APB bus.
– SPI controller, residing on the APB bus.
– Two SSP controllers with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt and pins. The SSP controllers can be used
with the GPDMA controller and reside on the APB bus.
UM10211
Chapter 1: Introductory information
Rev. 01 — 6 October 2006 User manual
UM10211_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 6 October 2006 4 of 612
Philips Semiconductors
UM10211
Chapter 1: LPC2300 Introductory information
– Three I
2
C Interfaces reside on the APB bus. The second and third I
2
C interfaces
are expansion I
2
Cs with standard port pins rather than special open drain I
2
C pins.
– I
2
S (Inter-IC Sound) interface for digital audio input or output, residing on the APB
bus. The I
2
S interface can be used with the GPDMA.
• Other APB Peripherals:
– Secure Digital (SD) / MultiMediaCard (MMC) memory card interface.
– Up to 70 (LPC2364/6/8) or 104 (LPC2378) general purpose I/O pins.
– 10 bit A/D converter with input multiplexing among 6 pins (LPC2364/66/68) or 8
pins LPC2378).
– 10 bit D/A converter.
– Four general purpose Timers with two capture inputs each and up to four compare
output pins each. Each Timer block has an external count input.
– One PWM/Timer block with support for 3 phase motor control. The PWM has two
external count inputs.
– Real Time Clock with separate power pin, clock source can be the RTC oscillator
or the APB clock.
– 2 kB Static RAM powered from the RTC power pin, allowing data to be stored
when the rest of the chip is powered off.
– Watchdog Timer. The watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator, or the APB clock.
• Standard ARM Test/Debug interface for compatibility with existing tools.
• Emulation Trace Module
• supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: Idle, Sleep, Power Down, and Deep Power down.
Four external interrupt inputs. In addition every PORT0/2 pin can be configured as an
edge sensing interrupt.
Processor wakeup from Power Down mode via any interrupt able to operate during
Power Down mode (includes external interrupts, RTC interrupt, and Ethernet wakeup
interrupt).
Two independent power domains allow fine tuning of power consumption based on
needed features.
Brownout detect with separate thresholds for interrupt and forced reset.
On-chip Power On Reset.
On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
4 MHz internal RC oscillator that can optionally be used as the system clock. For USB
and CAN application, an external clock source is suggested to be used.
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
Boundary scan for simplified board testing. (LPC2378 only)
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
UM10211_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 6 October 2006 5 of 612
Philips Semiconductors
UM10211
Chapter 1: LPC2300 Introductory information
3. Applications
• Industrial control
• Medical systems
4. Ordering options
5. Architectural overview
The LPC2300 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local
Bus for closely coupled, high speed access to the majority of on-chip memory, the AMBA
Advanced High-performance Bus (AHB) interfacing to high speed on-chip peripherals and
external memory, and the AMBA Advanced Peripheral Bus (APB) for connection to other
on-chip peripheral functions. The microcontroller permanently configures the
ARM7TDMI-S processor for little-endian byte order.
The microcontroller implements two AHB buses in order to allow the Ethernet block to
operate without interference caused by other system activity. The primary AHB, referred
to as AHB1, includes the Vectored Interrupt Controller, General Purpose DMA Controller,
External Memory Controller, USB interface, and a 8 kB SRAM primarily intended for use
by the USB.
The second AHB, referred to as AHB2, includes only the Ethernet block and an
associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary
AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into
off-chip memory or unused space in memory residing on AHB1.
Table 1. LPC2364/6/8/78 ordering options
Type number Flash
(kB)
SRAM(kB) Ethernet USB
dev +
4kB
FIFO
CAN SD/
MMC
GP
DMA
ADC DAC Temp
range
Local
bus
Ether.
buff
GP/
USB
RTC Total
LPC2364FB100 128 8 16 8 2 34 RMII yes 2 ch no yes 6 ch 1 ch −40 °C to
+85 °C
LPC2366FB100 256 32 16 8 2 58 RMII yes 2 ch no yes 6 ch 1 ch −40 °C to
+85 °C
LPC2368FB100 512 32 16 8 2 58 RMII yes 2 ch yes yes 6 ch 1 ch −40 °C to
+85 °C
Table 2. LPC2378 ordering options
Type number Flash
(kB)
SRAM(kB) Ext Bus Ether
net
USB
dev +
4kB
FIFO
CAN SD/
MMC
GP
DMA
ADC DAC Temp
range
Local bus
Ether. buff
GP/USB
RTC
Total
LPC2378FBD144 512 32 16 8 2 58 MiniBus:
8 data,
16 addr
& 2 cs
RMII yes 2 ch yes yes 8 ch 1 ch −40 °C to
+85 °C
