OV9650_datasheet

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OV9650_datasheet.pdf
Omn sion Section 6, Output Formatter 6. 1 Windowing 34 6.2 Data Formatting 35 6.2.1 TU-656 Format Enable 6.2.2 Frame Rate Adjust 36 6.2.3 Output Data MSB/LSB Swap Enable 37 6.2.4 D9: 0]-PCLK Reference Edge 37 Section 7, Digital Video Port 38 Section 8, Special Image Effects 38 Section 9, Preview Mode to Still Image Capture Sequence 39 9.1 Exposure Time and Gain Calculation 40 Section 10, SCCB Interface 40 10.1 Control functions 40 10.1.1 Register Reset 41 10.1.2 Standby Mode Enable 41 10.1.3 Tri-state Enable 10.2 Register Set Section 11, Prototyping and Evaluation Modules 53 11.1 OV9650EAA Prototyping Module 53 11.2 OV9650ECX USB 20 Evaluation module ....,53 Section 12 Lens selection,,.. 53 Section 13, oV9650 Bug List 53 Appendix A, Reference SCCB Settings 54 ersion 11. december 7. 2004 Proprietary to Omni vision Technologies ov9650 Color CMOS SXGA(1.3 MegaPixel) CameraChip TM Omn.sion List of Figures Figure 1-1 OV9650 Functional Block Diagram Figure 3-1 Manual Exposure Frame Drop Timing Diagram 13 Figure 3-2 Desired Convergence 1画国 17 Figure 3-3 SXGA Strobe Flash Timing Diagram 19 Figure 3-4 VGA Strobe Flash Timing Diagram 19 Figure 3-5 QVGA Strobe Flash Timing Diagram 19 Figure 5-1 Gamma Curve 25 Figure 5-2 Lens Shading Correction 31 Figure 6-1 EXample of Windowing 34 Figure 6-2 MSB/LSB Output Data Swap 37 Proprietary to Omni vision Technologies Version 1.1. December 7. 2004 Amnion List of tables Table 2-1 OV9650 Output Formats Table 2-2 Resolution Register Settings Table 3-1 Frame Rate, Pixel Clock Rate, and Input Clock Rate(CLKRC=0X81, 4X PLL). 11 Table 3-2 Banding Filter Value(Input Clock Frequency =12 MHz, 4X PLL) 16 Table 3-3 AEC Convergence Limits 17 Table 3-4 AEC Options 18 Table 4-1 Total gain to control bit correlation 21 Table 4-2 agc general controls 22 Table 4-3 AGc enable bit Table 4-4 AGC Convergence Limits 23 Table 4-5 AWb red/ blue balance control 24 Table 5-1 Related Registers and Parameters 25 Table 5-2 Color Matrix Related Registers and Parameters 27 Table 5-3 Color Matrix Related Registers and Parameters 30 Table 5-4 Lens Shading Correction Registers and Parameters 32 Table 6-1 Output Formatting general Controls 33 Table 6-2 RGB: 555 and RGB: 565 Output Format Controls Table 6-3 Windowing control registers 34 Table 6-4 Data Formatting 35 Table 7-1 Output Drive Current 38 Table 8-1 Special Image Effects 38 Table 10-1 SCCB Control functions :· 40 Table 10-2 Device Control Register List 42 ersion 11. december 7. 2004 Proprietary to Omni vision Technologies ov9650 Color CMOS SXGA(1.3 MegaPixel) CameraChip TM Omn colon 1 Introduction This general application note is provided as a brief overview of the settings required for programming the ov9650 CAMERACHIP. The Implementation Guide supplies the design engineer with quick-start tips for successful design solutions The ov9650 Datasheet provides complete information on the features, pin descriptions, and registers of the Ov9650. The Implementation Guide is intended to complement the Ov9650 Datasheet with considerations for PCB layout, register configurations, and timing parameters for rapid product design and deployment 1.1 Function Description Figure 1-1 shows the functional block diagram of the ov9650 image sensor. The ov9650 includes Image Sensor Array (1300 X 1028 resolution Timing generator Analog Processing Block Digital Signal Processor(DSP) Output Formatter Digital Video Port SCCB Interface Figure 1-1 ov9650 Functional Block Diagram Proprietary to Omni vision Technologies Version 1.1. December 7. 2004 Amnion Image Sensor Array 2 Image Sensor Array The ov9650 CAMERACHIP has an active image array size of 1300 columns by 1028 rows(1, 336, 400 pixels) The pixel cells themselves are identical, but have rgb color filters arranged in a line-alternating BG/GR Bayer Pattern The final YUVlYCb Cr image uses this filter pattern to interpolate each pixel's BG or gr color from the light striking the cell directly, as well as from the light striking the surrounding cells. The ' Raw RGB image does not have any image processing Table 2-1 lists all Ov9650 output formats Table 2-1 oV9650 Output Formats Device Format Output Register YUV/YCbCr 8 bits, 4: 2: 2(Interpolated color) COM7[2]=0(0x12 GRB 8 bits, 4: 2: 2(Interpolated color) COM7[2]=1(0×12),COM7[O]=0, COM15[4]=0(0×40) OV9650 RGB565 5-bitR. 6-bit G, 5-bit B cOM7[2]=1(0×12),COM7[o]=0, cOM154]=1(0X40),COM155]=0 RGB555 5-bitr.5-bit g.5-bit B COM72=1(0×12),cOM70]=0, cOM15[4]=1(0×40).cOM15[5=1 Raw rGB 10/8 bits(Bayer filter color) COM7[0=1(0×12),coM7[2]=1 ersion 11. december 7. 2004 Proprietary to Omni vision Technologies ov9650 Color CMOS SXGA(1.3 MegaPixel) CameraChip TM Omn colon 2.1 Resolution Formats The ov9650 CAMERACHIP supports SXGA(1280x1024), VGA (640X480), CIF (352x288), QVGA 320X240), QCIF(176x144), QQVGA (160X120)and QQCIF (88X72). The different register settings for different resolution formats are listed in table 2-2 Note: Contact your local OmniVision support engineer for OV9650 Reference SCCB settings. Sensor power-on default values are not the best settings for image quality Table 2-2. Resolution Register Settings(Sheet 1 of 2) Resolution Register Address Value Description(12 MHz Input Clock, 4X PLL) COM1(0×04) 0X00 COM3(0XOC) 0x00 COM4(0XOD) 0x00 CLKRC(0×11) 0X80 SXGA 15 fps sXGA YUV mode COM7(0×12) 0x00 ADC( 0X37) 0×81 ACOM(0X38 0x93 OFON (0X39) 0x50 COM1(0×04) 0x00 CoM30Xoc)0×04 COM4(OXOD) 0x80 CLKRO(0×11) 0x81 VGA 30 fps VGA YUV mode COM7(0×12) 0x40 ADC(0X37) 0x91 ACOM(0X38 0X12 OFON (0X39) 0x43 COM1(0x04) 0x00 COM3(0X0C) 0x04 COM4(0XOD) 0x80 CLKRC(0×11) 0×83 QVGA 30 tps QVGA YUV mode COM7(0×12) 0x10 ADC(0X37) 0x91 ACOM(0×38) 0x12 OFON (0X39) 0x43 Proprietary to Omni vision Technologies Version 11. december 7 2004 Omn sion Image Sensor Array Table 2-2. Resolution Register Settings Sheet 2 of 2) Resolution Register Address Value Description(12 MHz Input Clock, 4X PLL COM1(0×04) 0x24 COM3(0XOC) 0X04 COM4(0XOD) 0x80 CLKRC(0x 11) 0x83 QQVGA 30 fps QQVGA YL∨mode COM7(0×12) 0x10 ADC(0X37) 0x91 ACOM(0X38 0x12 OFON (0X39) 0x43 COM1(0x04) 0x00 CoM3(0×0C) 0x04 COM4(0XOD) 0x80 CLKRC(Ox 11) X83 CIF 30 tps CIF YUV mode COM7(0×12) 0x20 ADC( 0x37) 0x91 ACOM(0X38) 0x12 OFON(0X39) 0X43 COM1(0x04) 0x00 COM3(0XOC) 0x04 COM4(0XOD) 0x80 CLKRO(0×11) 0x87 QCIF 30 fps QCIF YUV mode COM7(0×12) 0x08 ADC( 0X37) 0x91 ACOM (0X38) 0x12 OFON(0×39) 0X43 COM1(0x04) 0x24 cOM3(0×0C) 0x04 COM4(0XOD) 0X80 CLKRC(0×11) 0x87 QQCIF 30 fps QQCIF YUV mode COM7(0×12) 0x08 ADC(0×37) 0x91 ACOM(0X38 0x12 OFON (0X39) 0×43 ersion 11. december 7. 2004 Proprietary to Omni vision Technologies ov9650 Color CMOS SXGA(1.3 MegaPixel) CameraChip TM Omn colon 3 Timing Generator In general, the timing generator controls the following functions Array Control and Frame Generation (SXGA, VGA, QVGA, QQVGA, CIF, QCIF and QQCIF outputs) Internal timing signal generation and distribution Frame Rate Timing Exposure Control External timing outputs(VSYNC, HREF/HSYNC, and PCLK) 3.1 Array Control and frame Generation 3.1.1 Frame Generation(SXGA, VGA, and lower resolutions) SXGA frame generation uses Progressive scanning of the array in which rows are sequentially read and transferred out to the aPb. The Raw rgb output preserves the Bayer Filter pattern so odd rows follow the pattern(BG)and even rows follow the pattern (Gr). Simple sub-sampling mode just skips every other two rows and every other two columns for VGA mode. The ov9650 has built-in Variopiyom technology to improve sub-sampled image resolution and reduce noise level Down-scaling technology down-scales the output size. VGA, QVGA, QQVGA, CIF, QCIf, and QQCIF have the same view angle which cuts 6.25% of the vertical view and keeps the same horizontal view of sXGa 3.2 Sync Signal selection The ov9650 CAMERACHIP supplies two output sync signals: VSYNC and HREF. The vertical sync (VSYNC) signal is output on pin D2. The horizontal reference signal (HREF)is output on pin E1 The HSYNc signal is available on pin E1(shares with HrEF When register COM10[6](0x15) value is set to The VSYNC and HSYNC signals are continuous. The HreF signal is only valid when there is active output data. If there is no output data, the href signal will remain at either high or low, depending on the polarity selection. The HsYNC/SYNC/HREF/PCLK polarity selection is controlled by register COM10[0, 1, 3, 4](0x15), respectively. Usually, an application uses the rising edge of PCLK to capture data when href is high The ov9650 can encode horizontal and vertical sync information into data set register COM1[6](0x04)high to enable the CCir656 format Refer to the ov9650 Datasheet for detailed signal timing information Proprietary to Omni vision Technologies Version 1.1. December 7. 2004

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