DA芯片TLC5615_tlc5615da转换设计资源-CSDN文库

共74个文件

lis：4个

o：4个

c：4个

atmega16

TLC5615

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DA-TLC5615.zip （74个子文件）

DA-TLC5615

TLC5615.pdf 245KB

SPI-TLC5615

spi_send.lis 5KB

main.c 372B

Last Loaded TLC5615.DBK 72KB

TLC5615.PWI 1KB

TLC5615.SRC 65B

spi_send.o 1KB

TLC5615.cof 2KB

TLC5615.mp 1KB

spi_send.h 150B

TLC5615.lk 20B

BACKUP

spi_send._c 479B

main.c.121218121410 373B

main.c.121216192738 209B

main.c.121218121430 372B

main._c 372B

main.c.121218120046 303B

main.c.121218120826 372B

main.c.121218121034 372B

spi_send.c.121218115932 486B

spi_send.c.121218120018 488B

main.c.121218120756 350B

main.c.121216192446 173B

main.lis 3KB

spi_send.c 450B

TLC5615.DSN 72KB

TLC5615.lst 6KB

TLC5615.dbg 799B

TLC5615.mak 1KB

main.o 775B

TLC5615.prj 1KB

TLC5615.hex 744B

moniSPI-TLC5615

spi_send.lis 5KB

TCL5615.cof 2KB

moni-TLC5615.PWI 1KB

Last Loaded moni-TLC5615.DBK 74KB

main.c 406B

TCL5615.dbg 904B

TCL5615.mp 1KB

TCL5615.lk 20B

spi_send.o 1KB

TCL5615.hex 760B

spi_send.h 222B

BACKUP

spi_send._c 616B

main.c.121216150756 142B

spi_send.c.121216152426 298B

spi_send.c.121216151718 171B

main.c.121216165604 406B

main.c.121216164500 411B

main.c.121216164510 400B

spi_send.c.121216160906 563B

spi_send.c.121216164124 626B

main.c.121216165120 400B

main._c 410B

main.c.121216164408 342B

spi_send.c.121216163300 619B

spi_send.c.121216155938 510B

spi_send.c.121216160802 548B

spi_send.c.121216165110 626B

spi_send.c.121216165554 610B

spi_send.c.121216151912 183B

main.c.121216151930 253B

spi_send.c.121216161624 599B

main.c.121216170522 406B

spi_send.c.121216161822 584B

main.c.121216164900 401B

main.lis 4KB

moni-TLC5615.DSN 74KB

spi_send.c 623B

TCL5615.mak 1KB

TCL5615.prj 1KB

TCL5615.SRC 65B

main.o 1KB

TCL5615.lst 6KB

TLC5615C, TLC5615I

10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS142C – OCTOBER 1996 – REVISED MARCH 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10-Bit CMOS Voltage Output DAC in an

8-Terminal Package

5-V Single Supply Operation

3-Wire Serial Interface

High-Impedance Reference Inputs

Voltage Output Range ...2 Times the

Reference Input Voltage

Internal Power-On Reset

Low Power Consumption . . . 1.75 mW Max

Update Rate of 1.21 MHz

Settling Time to 0.5 LSB . . . 12.5 µs Typ

Monotonic Over Temperature

Pin Compatible With the Maxim MAX515

applications

Battery-Powered Test Instruments

Digital Offset and Gain Adjustment

Battery Operated/Remote Industrial

Controls

Machine and Motion Control Devices

Cellular Telephones

description

The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high

impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is

monotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function is

incorporated to ensure repeatable start-up conditions.

Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to

industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to

produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital

communication protocols include the SPI, QSPI, and Microwire standards.

The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.

The TLC5615C is characterized for operation from 0°C to 70°C. The TLC5615I is characterized for operation

from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

†

(D)

PLASTIC SMALL OUTLINE

(DGK)

PLASTIC DIP

(P)

0°C to 70°C TLC5615CD TLC5615CDGK TLC5615CP

–40°C to 85°C TLC5615ID TLC5615IDGK TLC5615IP

†

Available in tape and reel as the TLC5615CDR and the TLC5615IDR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

DIN

SCLK

DOUT

OUT

REFIN

AGND

D, P, OR DGK PACKAGE

(TOP VIEW)

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

TLC5615C, TLC5615I

10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS142C – OCTOBER 1996 – REVISED MARCH 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

DAC

10-Bit DAC Register

Power-ON

Reset

Control

Logic

16-Bit Shift Register

Dummy

Bits

10 Data Bits

(LSB) (MSB)

REFIN

AGND

SCLK

DIN

OUT

(Voltage Output)

DOUT

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

DIN 1 I Serial data input

SCLK 2 I Serial clock input

CS 3 I Chip select, active low

DOUT 4 O Serial data output for daisy chaining

AGND 5 Analog ground

REFIN 6 I Reference input

OUT 7 O DAC analog voltage output

8 Positive power supply

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (V

to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to AGND – 0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range to AGND – 0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage at OUT from external source V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current at any terminal ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TLC5615C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC5615I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TLC5615C, TLC5615I

10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS142C – OCTOBER 1996 – REVISED MARCH 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

4.5 5 5.5 V

High-level digital input voltage, V

2.4 V

Low-level digital input voltage, V

0.8 V

Reference voltage, V

ref

to REFIN terminal 2 2.048 V

–2 V

Load resistance, R

2 kΩ

erating free air tem

erature T

TLC5615C 0 70 °C

Operating

free

air

temperat

TLC5615I –40 85 °C

electrical characteristics over recommended operating free-air temperature range, V

= 5 V ±5%,

ref

= 2.048 V (unless otherwise noted)

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 bits

Integral nonlinearity, end point adjusted (INL) V

ref

= 2.048 V, See Note 1 ±1 LSB

Differential nonlinearity (DNL) V

ref

= 2.048 V, See Note 2 ±0.1 ± 0.5 LSB

Zero-scale error (offset error at zero scale) V

ref

= 2.048 V, See Note 3 ±3 LSB

Zero-scale-error temperature coefficient V

ref

= 2.048 V, See Note 4 3 ppm/°C

Gain error V

ref

= 2.048 V, See Note 5 ±3 LSB

Gain-error temperature coefficient V

ref

= 2.048 V, See Note 6 1 ppm/°C

PSRR

Power su

ly rejection ratio

Zero scale

See Notes 7 and 8

PSRR

ppl

rejection

ratio

Gain

See

Notes

and

Analog full scale output R

= 100 kΩ 2V

ref

(1023/1024) V

NOTES: 1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text).

2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1

LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains

constant) as a change in the digital input code.

3. Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).

4. Zero-scale-error temperature coefficient is given by: E

TC = [E

max

) – E

min

)]/V

ref

× 10

/(T

max

– T

min

5. Gain error is the deviation from the ideal output (V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-scale

error.

6. Gain temperature coefficient is given by: E

TC = [E

max

) – E

min

)]/V

ref

× 10

/(T

max

– T

min

7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the V

from 4.5 V to 5.5 V dc and measuring the proportion of

this signal imposed on the zero-code output voltage.

8. Gain-error rejection ratio (EG-RR) is measured by varying the V

from 4.5 V to 5.5 V dc and measuring the proportion of this signal

imposed on the full-scale output voltage after subtracting the zero-scale change.

voltage output (OUT)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Voltage output range R

= 10 kΩ 0 V

–0.4 V

Output load regulation accuracy V

O(OUT)

= 2 V, R

= 2 kΩ 0.5 LSB

OSC

Output short circuit current OUT to V

or AGND 20 mA

OL(low)

Output voltage, low-level I

O(OUT)

≤ 5 mA 0.25 V

OH(high)

Output voltage, high-level I

O(OUT)

≤ –5 mA 4.75 V

TLC5615C, TLC5615I

10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS142C – OCTOBER 1996 – REVISED MARCH 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, V

= 5 V ±5%,

ref

= 2.048 V (unless otherwise noted) (continued)

reference input (REFIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage 0 V

–2 V

Input resistance 10 MΩ

Input capacitance 5 pF

digital inputs (DIN, SCLK, CS)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level digital input voltage 2.4 V

Low-level digital input voltage 0.8 V

High-level digital input current V

= V

±1 µA

Low-level digital input current V

= 0 ±1 µA

Input capacitance 8 pF

digital output (DOUT)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage, high-level I

= –2 mA V

–1 V

Output voltage, low-level I

= 2 mA 0.4 V

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

Supply voltage 4.5 5 5.5 V

Power su

ly current

= 5.5 V,

No load,

All inputs = 0 V or V

ref

= 0 150 250 µA

ppl

rrent

= 5.5 V,

No load,

All inputs = 0 V or V

ref

= 2.048 V 230 350 µA

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Signal-to-noise + distortion, S/(N+D)

ref

= 1 V

at 1 kHz + 2.048 Vdc,

code = 11 1111 1111,

See Note 9

60 dB

NOTE 9: The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate.

TLC5615C, TLC5615I

10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS142C – OCTOBER 1996 – REVISED MARCH 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

digital input timing requirements (see Figure 1)

PARAMETER MIN NOM MAX UNIT

su(DS)

Setup time, DIN before SCLK high 45 ns

h(DH)

Hold time, DIN valid after SCLK high 0 ns

su(CSS)

Setup time, CS low to SCLK high 1 ns

su(CS1)

Setup time, CS high to SCLK high 50 ns

h(CSH0)

Hold time, SCLK low to CS low 1 ns

h(CSH1)

Hold time, SCLK low to CS high 0 ns

w(CS)

Pulse duration, minimum chip select pulse width high 20 ns

w(CL)

Pulse duration, SCLK low 25 ns

w(CH)

Pulse duration, SCLK high 25 ns

output switching characteristic

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

pd(DOUT)

Propagation delay time, DOUT C

= 50 pF 50 ns

operating characteristics over recommended operating free-air temperature range, V

= 5 V ±5%,

ref

= 2.048 V (unless otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SR Output slew rate

= 100 pF,

= 25°C

= 10 kΩ,

0.3 0.5 V/µs

Output settling time

To 0.5 LSB,

= 10 kΩ,

= 100 pF,

See Note 10

12.5 µs

Glitch energy DIN = All 0s to all 1s 5



NOTE 10: Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of

000 hex to 3FF hex or 3FF hex to 000 hex.

reference input (REFIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Reference feedthrough REFIN = 1 V

at 1 kHz + 2.048 Vdc (see Note 11) –80 dB

Reference input

bandwidth (f–3dB)

REFIN = 0.2 V

+ 2.048 Vdc REFIN = 0.2 V

+ 2.048 Vdc 30 kHz

NOTE 11: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V

ref

input = 2.048 Vdc + 1 V

at 1 kHz.

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