简单verilog testbench
`timescale 1ns/1ns
module tb_jet_ctrl_top();
parameter U_DLY = 1;
integer i;
reg rst_n;
reg clk;
reg [ 7:0] cpu_dat;
reg [11:8] cpu_addr;
reg cpu_cs;
reg cpu_wr_n;
reg prt_trig_n;
initial begin
rst_n = 1'd0;
#100;
rst_n = 1'd1;
end
initial begin
clk = 1'd0;
