2018年最新版 1800-2017 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language（2018.8299595）
Abstract: The definition of the language syntax and tics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level(RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces(APIs) to foreign programming languages Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, IEEE 1800 TM, PLL, programming language interface, System Verilog, Verilog, VPI The Institute of Electrical and Electronics Engineers, Inc 3 Park Avenue. New york NY 10016-5997 USA Copyright o 201 8 by The Institute of Electrical and Electronics Engineers Inc All rights reserved. Published 21 February 2018. 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USers of this standard are expressly advised that determination of the validity of any patent rights, and the risk of infringement of such rights, is entirely their own responsibility Further information may be obtained from the Ieee Standards Association Copyrightc 2018 IEEE. All rights reserved Participants The System Verilog Language Working Group is entity based. At the time this standard was completed, the System Verilog Working Group had the following membership Karen Pieper, Accellera Systems Initiative, Chair Neil Korpusik, Oracle Corporation, vice Chair, Technical Chair Dennis Brophy, Mentor, a Siemens Business, Secretary Shalom bresticker, Accellera Systems Initiative, Editor Dave rich. Mentor. a Siemens business Matt Maidment, Intel Corporation Dmitry Korchemny, Synopsys, Inc Scott Little mentor a siemens business Michiel Ligthart, Design Automation, Inc Charles Dawson Cadence design Systems, Inc Work on this standard was divided among primary committees The Design and Testbench Committee(SV-BC) was responsible for the specification of the design and testbench features of System Verilog Matt Maidment. Intel Corporation, Chair Brad Pierce, Synopsys, Inc, CO-Chair Shalom Bresticker, Accellera Systems Initiative Justin Refice, NVIDIA Corporation Jonathan Bromley, Oracle Corporation Dave rich. mentor. a Siemens business Eric Coffin. Mentor a Siemens business Ray ryan, Mentor, a Siemens Business Mark Hartog, Synopsys, Inc Arturo Salz, Synopsys, Inc Neil Korpusik, Oracle Corporation Steven Sharp, Cadence Design Systems, Inc Francoise Martinolle, Cadence Design Systems, Inc Mark Strickland, Cisco Systems, Inc C. Venkat Ramana rao. Mentor a Siemens business Brandon Tipp. Intel Corporation The Assertions Committee(SV-AC) was responsible for the specification of the assertion features of System Verilog. Dmitry Korchemny, Synopsys, Inc, Chair Erik Seligman, Intel Corporation, Co-Chair Mehbub ali Intel corporation Ben Cohen, Accellera Systems Initiative Shalom Bresticker, Accellera Systems Initiative Manisha Kulshrestha, Mentor Graphics Corporation Eduard Cerny, Synopsys, Inc Anupam Prabhakar, Mentor Graphics Corporation Ang Boon Chong, Intel Cor Samik Sengupta, s The Discrete Committee(SV-DC)was responsible for defining features to support modeling of analog/ mixed-Signal circuit components in the discrete domain Scott Little Mentor. a Siemens Business chair Scott Cranston, Cadence Design Systems, Inc, Co-Chair Kevin Cameron, Samsung Arturo Salz, Synopsys, Inc Shekar Chetput, Cadence Design Systems, Inc Aaron Spratt, Cadence Design Systems, Inc Dave Cronauer, Synopsys, Inc Martin vlach. Mentor. a Siemens Business Mark Hartoog, Synopsys, Inc Gordon Vreugdenhil mentor. a Siemens business Copyright@ 2018 IEEE. All rights reserved The following members of the entity balloting committee voted on this standard. Bal loters may have voted for approval, disapproval, or abstention Accellera systems Initiative, Inc Oracle. Inc Cadence Design Systems, Inc Siemens Corporation Cisco Systems, Inc Synopsys, Inc Intel corporation Verific design Automation, Inc. When the IEEE-SA Standards Board approved this standard on 6 December 2017, it had the following membershi Jean-Philippe faure, chair Gary Hoffman, vice Chai John D. Kulick, Past Chair Konstantinos Karachalios, Secretary Chuck adams Thomas Koshy Robby robson Masayuki ariyoshi Joseph L. Koepfinger* Dorothy Stanley Ted burse Kevin lu Adrian Stephens Stephen dukes Daleep mohla Mehmet ulema Doug edwards Damir novosel Phil wennblom J. Travis griffith Ronald c. petersen Howard wolfman Michael janezic Annette D. Reill Yu Yuan 米 Member emeritus Copyright 2018 IEEE. All rights reserved Introduction his introduction is not part of IEEE Std 1800-2017, IEEE Standard for System Verilog-Unified Hardware Design, Specification, and Verification Language The purpose of this standard is to provide the electronic design automation(EDA), semiconductor, and system design communities with a well-defined and official IEEE unified hardware design, specification, and verification standard language. The language is designed to coexist and enhance the hardware description and verification languages(HDVLs) presently used by designers while providing the capabilities lacking in those languages System Verilog is a unified hardware design, specification, and verification language based on the Accellera System Verilog 3. 1a extensions to the Verilog hardware description language(HDL) B41, published in 2004. Accellera is a consortium of EDa, semiconductor, and system companies. IEEE Std 1800 enables a productivity boost in design and validation and covers design, simulation, validation, and formal assertion-based verification flows System Verilog enables the use of a unified language for abstract and detailed specification of the design specification of assertions, coverage, and testbench verification based on manual or automatic methodologies. System Verilog offers application programming interfaces (APIs) for coverage and assertions, and a direct programming interface(DPi) to access proprietary functionality. System Verilog offers methods that allow designers to continue to use present design languages when necessary to leverage existing designs and intellectual property (IP). This standardization project will provide the vlsi design engineers with a well-defined Ieee standard, which meets their requirements in design and validation, and which enables a step function increase in their productivity. This standardization project will also provide the eDa industry with a standard to which they can adhere and that they can support in order to deliver their solutions in this area Copyright@ 2018 IEEE. All rights reserved Contents Part One: Design and verification Constructs Overview ..38 1.1 Scope 38 1. 2 Purpose 38 1.3 Content summary 38 4 Special terms… 1.5 Conventions used in this standard .39 1.6 Syntactic description 40 1.7 Use of color in this standard 1. 8 Contents of this standard 1. 9 Deprecated clauses 44 1.10 Examples 1.11 Prerequisites…… 44 Normative references 45 Design and verification building blocks 47 3. 1 General 47 3.2 Design elements 47 3. 3 Modules ++++,,,,+ ++++“+++++++++ 3.4 Progr 48 3.5 Interf 3.6 Checks ··· 50 3.7 Primitives 50 3. 8 Subrout 3.9 Packa 50 3.10 Configurations.... 3.11 3.12 Compilation and elaboration..... 3.13 Name spaces 3.14 Simulation time units and precision Scheduling semantics 4.1 General 4.2 Execution of a hardware model and its verification environment 4.3 Event simulation ·, 4.4 Stratified event scheduler 4.5 System Verilog simulation reference algorithm..... 65 4.6 Determinism 4.7 Nondeterminism 66 4.8 Race conditions…… Copyright@ 2018 IEEE. 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