/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name : stm32f10x_tim1.c
* Author : MCD Application Team
* Version : V1.0
* Date : 10/08/2007
* Description : This file provides all the TIM1 software functions.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_tim1.h"
#include "stm32f10x_rcc.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ TIM1 registers bit address in the alias region ----------- */
#define TIM1_OFFSET (TIM1_BASE - PERIPH_BASE)
/* --- TIM1 CR1 Register ---*/
/* Alias word address of CEN bit */
#define CR1_OFFSET (TIM1_OFFSET + 0x00)
#define CEN_BitNumber 0x00
#define CR1_CEN_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (CEN_BitNumber * 4))
/* Alias word address of UDIS bit */
#define UDIS_BitNumber 0x01
#define CR1_UDIS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (UDIS_BitNumber * 4))
/* Alias word address of URS bit */
#define URS_BitNumber 0x02
#define CR1_URS_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (URS_BitNumber * 4))
/* Alias word address of OPM bit */
#define OPM_BitNumber 0x03
#define CR1_OPM_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (OPM_BitNumber * 4))
/* Alias word address of ARPE bit */
#define ARPE_BitNumber 0x07
#define CR1_ARPE_BB (PERIPH_BB_BASE + (CR1_OFFSET * 32) + (ARPE_BitNumber * 4))
/* --- TIM1 CR2 Register --- */
/* Alias word address of CCPC bit */
#define CR2_OFFSET (TIM1_OFFSET + 0x04)
#define CCPC_BitNumber 0x00
#define CR2_CCPC_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCPC_BitNumber * 4))
/* Alias word address of CCUS bit */
#define CCUS_BitNumber 0x02
#define CR2_CCUS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCUS_BitNumber * 4))
/* Alias word address of CCDS bit */
#define CCDS_BitNumber 0x03
#define CR2_CCDS_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (CCDS_BitNumber * 4))
/* Alias word address of TI1S bit */
#define TI1S_BitNumber 0x07
#define CR2_TI1S_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (TI1S_BitNumber * 4))
/* Alias word address of OIS1 bit */
#define OIS1_BitNumber 0x08
#define CR2_OIS1_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1_BitNumber * 4))
/* Alias word address of OIS1N bit */
#define OIS1N_BitNumber 0x09
#define CR2_OIS1N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS1N_BitNumber * 4))
/* Alias word address of OIS2 bit */
#define OIS2_BitNumber 0x0A
#define CR2_OIS2_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2_BitNumber * 4))
/* Alias word address of OIS2N bit */
#define OIS2N_BitNumber 0x0B
#define CR2_OIS2N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS2N_BitNumber * 4))
/* Alias word address of OIS3 bit */
#define OIS3_BitNumber 0x0C
#define CR2_OIS3_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3_BitNumber * 4))
/* Alias word address of OIS3N bit */
#define OIS3N_BitNumber 0x0D
#define CR2_OIS3N_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS3N_BitNumber * 4))
/* Alias word address of OIS4 bit */
#define OIS4_BitNumber 0x0E
#define CR2_OIS4_BB (PERIPH_BB_BASE + (CR2_OFFSET * 32) + (OIS4_BitNumber * 4))
/* --- TIM1 SMCR Register --- */
/* Alias word address of MSM bit */
#define SMCR_OFFSET (TIM1_OFFSET + 0x08)
#define MSM_BitNumber 0x07
#define SMCR_MSM_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (MSM_BitNumber * 4))
/* Alias word address of ECE bit */
#define ECE_BitNumber 0x0E
#define SMCR_ECE_BB (PERIPH_BB_BASE + (SMCR_OFFSET * 32) + (ECE_BitNumber * 4))
/* --- TIM1 EGR Register --- */
/* Alias word address of UG bit */
#define EGR_OFFSET (TIM1_OFFSET + 0x14)
#define UG_BitNumber 0x00
#define EGR_UG_BB (PERIPH_BB_BASE + (EGR_OFFSET * 32) + (UG_BitNumber * 4))
/* --- TIM1 CCER Register --- */
/* Alias word address of CC1E bit */
#define CCER_OFFSET (TIM1_OFFSET + 0x20)
#define CC1E_BitNumber 0x00
#define CCER_CC1E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1E_BitNumber * 4))
/* Alias word address of CC1P bit */
#define CC1P_BitNumber 0x01
#define CCER_CC1P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1P_BitNumber * 4))
/* Alias word address of CC1NE bit */
#define CC1NE_BitNumber 0x02
#define CCER_CC1NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NE_BitNumber * 4))
/* Alias word address of CC1NP bit */
#define CC1NP_BitNumber 0x03
#define CCER_CC1NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC1NP_BitNumber * 4))
/* Alias word address of CC2E bit */
#define CC2E_BitNumber 0x04
#define CCER_CC2E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2E_BitNumber * 4))
/* Alias word address of CC2P bit */
#define CC2P_BitNumber 0x05
#define CCER_CC2P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2P_BitNumber * 4))
/* Alias word address of CC2NE bit */
#define CC2NE_BitNumber 0x06
#define CCER_CC2NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NE_BitNumber * 4))
/* Alias word address of CC2NP bit */
#define CC2NP_BitNumber 0x07
#define CCER_CC2NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC2NP_BitNumber * 4))
/* Alias word address of CC3E bit */
#define CC3E_BitNumber 0x08
#define CCER_CC3E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3E_BitNumber * 4))
/* Alias word address of CC3P bit */
#define CC3P_BitNumber 0x09
#define CCER_CC3P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3P_BitNumber * 4))
/* Alias word address of CC3NE bit */
#define CC3NE_BitNumber 0x0A
#define CCER_CC3NE_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NE_BitNumber * 4))
/* Alias word address of CC3NP bit */
#define CC3NP_BitNumber 0x0B
#define CCER_CC3NP_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC3NP_BitNumber * 4))
/* Alias word address of CC4E bit */
#define CC4E_BitNumber 0x0C
#define CCER_CC4E_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4E_BitNumber * 4))
/* Alias word address of CC4P bit */
#define CC4P_BitNumber 0x0D
#define CCER_CC4P_BB (PERIPH_BB_BASE + (CCER_OFFSET * 32) + (CC4P_BitNumber * 4))
/* --- TIM1 BDTR Register --- */
/* Alias word address of MOE bit */
#define BDTR_OFFSET (TIM1_OFFSET + 0x44)
#define MOE_BitNumber 0x0F
#define BDTR_MOE_BB (PERIPH_BB_BASE + (BDTR_OFFSET * 32) + (MOE_BitNumber * 4))
/* --- TIM1 CCMR1 Register --- */
/* Alias word address of OC1FE bit */
#define CCMR1_OFFSET (TIM1_OFFSET + 0x18)
#define OC1FE_BitNumber 0x02
#define CCMR1_OC1FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1FE_BitNumber * 4))
/* Alias word address of OC1PE bit */
#define OC1PE_BitNumber 0x03
#define CCMR1_OC1PE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1PE_BitNumber * 4))
/* Alias word address of OC1CE bit */
#define OC1CE_BitNumber 0x07
#define CCMR1_OC1CE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC1CE_BitNumber * 4))
/* Alias word address of OC2FE bit */
#define OC2FE_BitNumber 0x0A
#define CCMR1_OC2FE_BB (PERIPH_BB_BASE + (CCMR1_OFFSET * 32) + (OC2FE
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STM32-无刷直流电机控制器程序
共108个文件
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c:35个
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基于STM32的无刷直流控制器代码。完整代码。
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STM32-无刷直流电机控制器程序 (108个子文件)
milldrive_Opt.Bak 10KB
milldrive_Uv2.Bak 4KB
stm32f10x_tim1.c 111KB
stm32f10x_tim.c 97KB
stm32f10x_adc.c 54KB
stm32f10x_i2c.c 44KB
stm32f10x_rcc.c 42KB
stm32f10x_usart.c 33KB
stm32f10x_flash.c 32KB
stm32f10x_can.c 31KB
stm32f10x_it.c 30KB
stm32f10x_nvic.c 28KB
stm32f10x_spi.c 25KB
stm32f10x_dma.c 23KB
stm32f10x_gpio.c 21KB
MC_Keys.c 18KB
stm32f10x_svpwm_ics.c 18KB
LCD_4bit.c 13KB
stm32f10x_rtc.c 12KB
stm32f10x_rtc.c 12KB
main.c 11KB
stm32f10x_hall.c 11KB
stm32f10x_pwr.c 11KB
stm32f10x_bkp.c 11KB
stm32f10x_svpwm_3shunt.c 10KB
stm32f10x_exti.c 8KB
stm32f10x_MCdac.c 8KB
MC_Display.c 8KB
stm32f10x_wwdg.c 8KB
stm32f10x_systick.c 7KB
stm32f10x_lib.c 7KB
stm32f10x_iwdg.c 6KB
MC_PID_regulators.c 6KB
MC_Keys.c 5KB
MC_MotorControl_Layer.c 5KB
MC_Globals.c 3KB
timer.c 2KB
milldrive_millmotor.dep 35KB
milldrive_Target 1.dep 226B
stm32f10x_tim1.h 34KB
stm32f10x_tim.h 28KB
stm32f10x_map.h 20KB
stm32f10x_adc.h 16KB
stm32f10x_nvic.h 16KB
stm32f10x_i2c.h 15KB
stm32f10x_rcc.h 13KB
stm32f10x_gpio.h 12KB
stm32f10x_dma.h 12KB
stm32f10x_can.h 12KB
stm32f10x_usart.h 11KB
stm32f10x_flash.h 10KB
MC_Control_Param.h 9KB
stm32f10x_spi.h 9KB
stm32f10x_lcd.h 7KB
MC_State_Observer_param.h 6KB
MC_PMSM_motor_param.h 6KB
stm32f10x_exti.h 6KB
STM32F10x_MCconf.h 5KB
stm32f10x_conf.h 5KB
MC_const.h 5KB
MC_qmath.h 4KB
MC_hall_prm.h 4KB
stm32f10x_bkp.h 4KB
stm32f10x_lib.h 4KB
stm32f10x_pwr.h 4KB
MC_encoder_param.h 4KB
stm32f10x_rtc.h 4KB
MC_type.h 3KB
stm32f10x_iwdg.h 3KB
stm32f10x_type.h 3KB
MC_pwm_3shunt_prm.h 3KB
stm32f10x_it.h 3KB
stm32f10x_systick.h 3KB
MC_Globals.h 3KB
stm32f10x_MClib.h 3KB
MC_pwm_ics_prm.h 3KB
stm32f10x_dbg.h 3KB
stm32f10x_MCdac.h 3KB
stm32f10x_wwdg.h 3KB
MC_MotorControl_Layer.h 2KB
MC_State_Observer.h 2KB
stm32f10x_hall.h 2KB
MC_Clarke_Park.h 2KB
stm32f10x_svpwm_3shunt.h 2KB
cortexm3_macro.h 2KB
MC_PID_regulators.h 2KB
stm32f10x_svpwm_ics.h 2KB
MC_State_Observer_Interface.h 2KB
stm32f10x_encoder.h 2KB
MC_Display.h 2KB
MC_FOC_Drive.h 2KB
stm32f10x_Timebase.h 2KB
LCD.h 1KB
timer.h 856B
MC_Keys.h 731B
CONST.h 109B
RAM.ini 362B
display.JPG 4KB
STM32F10x.lst 36KB
stm32f10x_vector.lst 30KB
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