PEX8733, PCI Express Gen 3 Switch, 32 Lanes, 18 Ports
© PLX Technology, www.plxtech.com Page 1 of 5 22Aug11, version 1.0
Highlights
PEX8733 General Features
o 32-lane, 18-port PCIe Gen 3 switch
- Integrated 8.0 GT/s SerDes
o 27 x 27mm
2
, 676-pin FCBGA package
o Typical Power: 6.4 Watts
PEX8733 Key Features
o Standards Compliant
- PCI Express Base Specification, r3.0
(compatible w/ PCIe r1.0a/1.1 & 2.0)
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control
o High Performance
performancePAK
Read Pacing (bandwidth throttling)
Multicast
Dynamic Buffer/FC Credit Pool
- Non-blocking switch fabric
- Full line rate on all ports
- Packet Cut-Thru with 132ns max packet
latency (x8 to x8)
- 2KB Max Payload Size
o Integrated DMA Engine
- Four DMA Channels
- Internal Descriptor Support
- DMA function independent from
transparent switch function
- 64-bit Addressing
- Pre-fetch Descriptor Mode
- Stride Mode
o Multi-Host & Fail-Over Support
- 2 Configurable Non-Transparent ports
- Failover with Non-Transparent port
- Up to 4 upstream/Host ports with 1+1 or
N+1 failover to other upstream ports
o Quality of Service (QoS)
- Two Virtual Channels
- Eight traffic classes per port
- Weighted round-robin source
port arbitration
o Reliability, Availability, Serviceability
visionPAK
Per Port Performance Monitoring
SerDes Eye Capture
PCIe Packet Generator
Error Injection and Loopback
- 3 Hot-Plug Ports with native HP Signals
- All ports hot-plug capable thru I
2
C
- SSC Isolation on up to 8 ports
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- Advanced Error Reporting
- Port Status bits and GPIO available
- JTAG AC/DC boundary scan
The ExpressLane™ PEX8733 device offers Multi-Host PCI Express switching
capability enabling users to connect multiple hosts to their respective
endpoints via scalable, high bandwidth, non-blocking interconnection to a
wide variety of applications including servers, storage, communications, and
graphics platforms. The PEX8733 is well suited for fan-out, aggregation,
and peer-to-peer traffic patterns.
Multi-Host Architecture
The PEX8733 employs an enhanced version of PLX’s field tested PEX8732
PCIe switch architecture, which allows users to configure the device in legacy
single-host mode or multi-host mode with up to four host ports capable of 1+1
(one active & one backup) or N+1 (N active & one backup) host failover. This
powerful architectural enhancement enables users to build PCIe based systems
to support high-availability, failover, redundant, or clustered systems.
High Performance & Low Packet Latency
The PEX8733 architecture supports packet cut-thru with a maximum
latency of 132ns (x8 to x8). This, combined with large packet memory,
flexible common buffer/FC credit pool and non-blocking internal switch
architecture, provides full line rate on all ports for performance-hungry
applications such as servers and switch fabrics. The low latency enables
applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes,
enabling the user to achieve even higher throughput.
Integrated DMA Engine
The PEX8733 boasts a versatile and powerful built-in DMA engine. The
DMA engine removes the burden of having to move data between devices
away from the processor – allowing the processor to perform computational
tasks instead. The four DMA channels can support high data rate transfers
between I/O devices connected to any of the switch’s ports. Additionally, the
DMA engine in the PEX8733 can be used to complement the DMA engine in
the processor by providing additional DMA channels for higher performance.
Data Integrity
The PEX8733 provides end-to-end CRC (ECRC) protection and Poison bit
support to enable designs that require end-to-end data integrity. PLX also
supports data path parity and memory (RAM) error correction circuitry
throughout the internal data paths as packets pass through the switch.
Flexible Configuration
The PEX8733’s 18 ports can be
configured to lane widths of x1, x2, x4,
x8, or x16. Flexible buffer allocation,
along with the device's flexible packet
flow control, maximizes throughput for
applications where more traffic flows in
the downstream, rather than upstream,
direction. Any port can be designated as
the upstream port, which can be changed
dynamically. Figure 1 shows some of the
PEX8733’s common port configurations
in legacy Single-Host mode.
