cadence官方encounter升级版本工具innovus user guide
Innoyus User guide Table of contents Contents About this manual 32 Audience 32 How This manual ls organized 32 Conventions Used in this manual 33 Related documents 34 Additional Learning Resources 35 37 Product and licensing Information 37 Overview 37 Innovus System Products and product options 38 Innovus Implementation System 38 Virtuoso Digital Implementation and First Encounter Product Packaging 40 Product Options 42 Licensing Terminology 45 Optional license requirement for 10/20/32nm Nodes 49 2 50 Flows 50 Design Implementation Flow 51 Introduction 52 Recommended Timing closure flow 53 Software 53 Foundation Flow 54 Data preparation and validation 54 Flow Preparation 61 Pre-Placement Optimization 64 Floorplanning and Initial Placement 64 May 2015 Product version 15. 1 Innovus User Guide Table of contents PreCTS Optimization 69 Clock Tree Synthesis 75 PostC TS Optimization 77 Detailed Routing 81 PostRoute Optimization 84 Chip finishing 88 Timing Sign Off 90 Final Timing Analysis and Optimization using Tempus/Quantus 91 Additional resources 91 Hierarchical and prototyping flow 92 Introduction 92 Top-down and Bottom-up Hierarchical Methodologies 94 Hierarchical Floorplan Considerations 96 Hierarchical Partitioning Flow and Capabilities 98 Chip planning 101 Supporting Giga-Scale Designs in Planning stage 114 Top-level Timing closure 114 Chip assembly 116 120 Infrastructure Related Capabilities 120 Getting Started 121 Product and Installation Information 121 Setting the Run-Time Environment 121 Temporary File locations 122 Open Access 123 Launching the console 123 T ab completing Command Names, Parameter Names, Global variable Names and Enum Values 123 Command-Line Editing 125 Setting Preferences 129 May 2015 Product version 15. 1 Innovus User Guide Table of contents Starting the software 131 Interrupting the Software 131 Using the log file viewer 134 Accessing Documentation and Help 135 Customizing the user Interface 142 Overview 142 Creating a New Menu 143 Modifying an Existing Menu 144 Adding a new toolbar and toolbutton 147 Querying and configuring interface elements 149 Accelerating the Design Process By Using Multiple-CPU Processing 151 Overview 151 Running Distributed Processing 154 Running Multi-Threading 154 Running Superthreading 155 Memory and Run Time Control 155 Checking the Distributed computing Environment 157 Setting and Changing the License Check-Out Order 157 Limiting the Multi-CPU License Search to Specific Products 158 Releasing licenses before the session Ends 158 Controlling the Level of Usage Information in the Log File 158 Where to Find More Information on Multi-CPU Licensing 159 Data Preparation 159 Generating a Technology file 160 Preparing Physical Libraries 160 Unsupported LEF and DEF Syntax 161 Generating the l/O Assignment File 165 Preparing Timing Libraries 189 Encrypting Libraries 189 Preparing Timing Constraints 189 Preparing Capacitance T ables 190 May 2015 Product version 15. 1 Innovus User Guide Table of contents Preparing Data for Delay calculation 190 Preparing data for crosstalk analysis 190 Checking Designs 190 Preparing Data in the Timing Closure Design Flow 191 Converting iPRT Format to LEF 191 Importing and Exporting Designs 191 Overview 193 Verifying Data before Importing a Design 194 Preparing the Design Netlist 194 The init design Import Flow 194 Importing Designs using the GUI 198 Loading a previously saved global variables file 200 Handling verilog assigns 201 Configuring the Setup for Multi-Mode Multi-Corner Analysis 201 Saving Designs 214 Loading and Saving Design Data 215 Converting an Innovus database to gdsl Stream or OaSis Format 219 About the gdsl Stream or oasiS Map File 225 Updating Files During an Innovus Session 235 SKILL to TCL Mapping 236 239 Design Planning Capabilities 239 Floorplanning the design 240 Overview 241 Common Floorplanning Sequence 242 Viewing the Floorplan 243 Module Constraint Types 245 Grouping Instances 250 Creating and Editing Rows 256 Using Vertical Rows 257 May 2015 Product version 15. 1 Innovus User Guide Table of contents Using Mul tiple-height Rows 260 Performing l/O Row Based Pad Placement 271 Editing pins 278 Running Relative Floorplanning 287 Saving and loading floorplan data 290 Snapping the Floorplan 291 Resizing the floorplan 293 Checking the Floorplan 304 FinFET Technology 306 Related Topics 310 Using Structured Data Paths 311 Overview 311 Benefits of Using SDP 312 General sDP Flow 314 Support for High-Speed Flip Flop columns 315 SDP Placement flow 317 Implementing SDP Capability 323 SDP Relative Placement File 324 Aligning SDPs by Pins 336 Setting SDP Options 338 Optimizing a Design with SDPs 340 Checking SDP Placement 342 Bus planning 343 Overview 343 Bus planning flow in Innovus 344 Creating a bus guide 345 Moving and stretching a bus guide 354 Cutting, Splitting, and Merging Bus Guides 354 Customizing the Bus guide display 356 Saving and restoring Bus Guide Information 358 Verifying Bus Guide 358 May 2015 Product version 15. 1 Innovus User Guide Table of contents Limitations of Bus Planning 358 Power Planning and Routing 360 Overview 360 Before You begin 361 Results 361 Loading, Saving, and Updating Special Route 362 Global Net connections 362 Creating a ring with User Defined coordinates 364 Fixing LEF Minimum Spacing Violations 365 Adding stripes to power domains 365 Adding Stripe in Multi-CPU mode 367 5 368 Design Implementation Capabilities 368 Low Power Design 369 Overview 371 Power Domain shutdown and scaling 371 Support for the Common Power Format (CPF) 373 Support for lEEE1 801 376 Flow Special handling for low power 382 Multiple supply voltage Top-Down Hierarchical Flow 400 Example of block-Level cPf generated by innovus 406 Example of Top-Level CPF Generated by Innovus 410 Multiple Supply Voltage Bottom-Up Hierarchical Flow 414 Leakage Power Optimization Techniques 417 Power Shutdown Techniques 421 Power Switch Optimization 447 Power Switch Prototyping 449 Placing the Design 457 Overview 458 Loading a design 458 May 2015 Product version 15. 1 Innovus User Guide Table of contents Preparing for Placement 458 Guiding Placement With Blockages 459 Adding Well-Tap cells 461 Adding End-Cap Cells 462 Placing Spare Cells and Spare Modules 465 Adding Padding 471 Placing Standard Cells 474 Running Placement in Multi-CPU Mode 475 Checking Placement 478 Adding filler cells 480 Placing Gate Array Style Filler Cells for Post-Mask ECO 481 Adding decoupling capacitance 482 Adding Logical Tie-Off Cells 483 Saving placement data 483 Specifying and Placing JTAG and Other Cells Close to the VOs 483 Optimizing and Reordering Scan Chains 484 Clock Tree Synthesis 497 The Clock Tree Synthesis Engines 498 Overview 500 Flow and Quick Start 502 Configuration and Method 506 Concepts and Clock Tree Specification 517 Reporting 540 CCOpt Clock Tree Debugger 547 Additional Topics 557 CCOpt Property System 563 Migrating from FE-cts 567 Legacy fE-cts flow 569 Legacy FE-CTS Capabilities 574 Before You begin 577 Results 577 May 2015 Product version 15. 1 Innovus User Guide Table of contents Understanding the cts Operation Modes 577 How cts calculates skew values 580 mproving postroute correlation 581 Specifying Macro Model Delays 582 Grouping clocks 586 Analyzing hierarchical clock trees 586 Module placement utilization 588 Clock Designs with Tight area 588 Balancing Pins for Macro Models 588 Timing model requirement for cells 588 Delay variation and ocv 588 Understanding PostC TS Clock Tree Optimization 590 Creating a clock Tree specification File 593 CTS Report Descriptions 644 Supported SDC Constraints 649 Working with Clock Mesh Structures 651 Overview 651 Clock Meshes versus clock trees 651 Creating Clock Meshes 654 Multispine Clock Mesh 664 Optimizing Timing 665 Overview 667 Before You begin 668 Results 668 nterrupting Timing optimization 670 Performing Optimization Before Clock Tree Synthesis 671 Performing postc ts optimization 674 Performing PostRoute Optimization 678 Optimizing Power during optDesign 683 Using useful Skew 687 Distributed Timing Analysis for Hold Fixing 689 May 2015 10 Product version 15. 1