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利用fpga实现的DDS,可输出正弦波,输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
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利用fpga实现的DDS,可输出正弦波,输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
-----------------------------------------------------------------------------
-- Project Name : NCO
--
-- Author : Bluetea
-- Creation Date : 03/11/04 18:20:21
-- Version Number : 1.0
-- Description :
-- This module will load the frequency word into the phase accumulator
-- synchronously at the proper pipeline timing. The input to this module
-- will be the frequency word and load write strobe. The output will be
-- the synchronous frequency word.
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY loadfw IS
PORT(
SYSCLK : IN STD_LOGIC; -- system clock input
RESETN : IN STD_LOGIC; -- global reset
FWWRN : IN STD_LOGIC; -- low asserted frequency word write strobe
FREQWORD : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- input frequency word from external pins
SYNCFREQ : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- synchronous frequency word
);
END loadfw;
ARCHITECTURE Load OF loadfw IS
-----------------------------------------------------------------------------
-- Project Name : NCO
--
-- Author : Bluetea
-- Creation Date : 03/11/04 18:20:21
-- Version Number : 1.0
-- Description :
-- This module will load the frequency word into the phase accumulator
-- synchronously at the proper pipeline timing. The input to this module
-- will be the frequency word and load write strobe. The output will be
-- the synchronous frequency word.
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY loadfw IS
PORT(
SYSCLK : IN STD_LOGIC; -- system clock input
RESETN : IN STD_LOGIC; -- global reset
FWWRN : IN STD_LOGIC; -- low asserted frequency word write strobe
FREQWORD : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- input frequency word from external pins
SYNCFREQ : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) -- synchronous frequency word
);
END loadfw;
ARCHITECTURE Load OF loadfw IS
SIGNAL fwreg : STD_LOGIC_VECTOR (31 DOWNTO 0);-- input frequency word registered
SIGNAL fwwrnm : STD_LOGIC; -- meta-stable frequency word write strobe
SIGNAL fwwrns : STD_LOGIC ; -- synchronous frequency word write strobe
SIGNAL loadp1, loadp2, loadp3, loadp4 : STD_LOGIC; -- synchronous load strobes
SIGNAL pipefw1, pipefw2, pipefw3, pipefw4 : STD_LOGIC_VECTOR (7 DOWNTO 0); -- pipelined FW registered values
BEGIN
SYNCFREQ <= pipefw4 & pipefw3 & pipefw2 & pipefw1;
-- register the input phase word
Reginphaword:process(FWWRN,RESETN)
begin
if RESETN='1' then
fwreg <=(others=>'0');
else
fwreg <= FREQWORD;
end if;
end process;
-- get a synchronous load strobe on the rising edge of PWWRN
Getstrobe:process(SYSCLK,RESETN)
begin
if SYSCLK'event and SYSCLK='1' then
if RESETN='1' then
fwwrnm <= '1';
fwwrns <= '1';
loadp1 <= '0';
loadp2 <= '0';
loadp3 <= '0';
loadp4 <= '0';
pipefw1 <=(others=>'0');
SIGNAL fwwrnm : STD_LOGIC; -- meta-stable frequency word write strobe
SIGNAL fwwrns : STD_LOGIC ; -- synchronous frequency word write strobe
SIGNAL loadp1, loadp2, loadp3, loadp4 : STD_LOGIC; -- synchronous load strobes
SIGNAL pipefw1, pipefw2, pipefw3, pipefw4 : STD_LOGIC_VECTOR (7 DOWNTO 0); -- pipelined FW registered values
BEGIN
SYNCFREQ <= pipefw4 & pipefw3 & pipefw2 & pipefw1;
-- register the input phase word
Reginphaword:process(FWWRN,RESETN)
begin
if RESETN='1' then
fwreg <=(others=>'0');
else
fwreg <= FREQWORD;
end if;
end process;
-- get a synchronous load strobe on the rising edge of PWWRN
Getstrobe:process(SYSCLK,RESETN)
begin
if SYSCLK'event and SYSCLK='1' then
if RESETN='1' then
fwwrnm <= '1';
fwwrns <= '1';
loadp1 <= '0';
loadp2 <= '0';
loadp3 <= '0';
loadp4 <= '0';
pipefw1 <=(others=>'0');
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- mingheui2014-06-18不能实现功能
u010391472
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