MSP430x2xx Family
User's Guide
Literature Number: SLAU144J
December 2004–Revised July 2013
Contents
Preface ...................................................................................................................................... 21
1 Introduction ...................................................................................................................... 23
1.1 Architecture ................................................................................................................. 24
1.2 Flexible Clock System .................................................................................................... 24
1.3 Embedded Emulation ..................................................................................................... 25
1.4 Address Space ............................................................................................................. 25
1.4.1 Flash/ROM ........................................................................................................ 25
1.4.2 RAM ................................................................................................................ 26
1.4.3 Peripheral Modules ............................................................................................... 26
1.4.4 Special Function Registers (SFRs) ............................................................................ 26
1.4.5 Memory Organization ............................................................................................ 26
1.5 MSP430x2xx Family Enhancements .................................................................................... 27
2 System Resets, Interrupts, and Operating Modes .................................................................. 28
2.1 System Reset and Initialization .......................................................................................... 29
2.1.1 Brownout Reset (BOR) .......................................................................................... 29
2.1.2 Device Initial Conditions After System Reset ................................................................. 30
2.2 Interrupts .................................................................................................................... 31
2.2.1 (Non)-Maskable Interrupts (NMI) ............................................................................... 31
2.2.2 Maskable Interrupts .............................................................................................. 34
2.2.3 Interrupt Processing .............................................................................................. 35
2.2.4 Interrupt Vectors .................................................................................................. 37
2.3 Operating Modes .......................................................................................................... 38
2.3.1 Entering and Exiting Low-Power Modes ...................................................................... 40
2.4 Principles for Low-Power Applications .................................................................................. 40
2.5 Connection of Unused Pins .............................................................................................. 41
3 CPU ................................................................................................................................. 42
3.1 CPU Introduction .......................................................................................................... 43
3.2 CPU Registers ............................................................................................................. 44
3.2.1 Program Counter (PC) ........................................................................................... 44
3.2.2 Stack Pointer (SP) ................................................................................................ 45
3.2.3 Status Register (SR) ............................................................................................. 45
3.2.4 Constant Generator Registers CG1 and CG2 ................................................................ 46
3.2.5 General-Purpose Registers R4 to R15 ........................................................................ 47
3.3 Addressing Modes ......................................................................................................... 47
3.3.1 Register Mode .................................................................................................... 49
3.3.2 Indexed Mode ..................................................................................................... 50
3.3.3 Symbolic Mode ................................................................................................... 51
3.3.4 Absolute Mode .................................................................................................... 52
3.3.5 Indirect Register Mode ........................................................................................... 53
3.3.6 Indirect Autoincrement Mode ................................................................................... 54
3.3.7 Immediate Mode .................................................................................................. 55
3.4 Instruction Set .............................................................................................................. 56
3.4.1 Double-Operand (Format I) Instructions ....................................................................... 57
3.4.2 Single-Operand (Format II) Instructions ....................................................................... 58
3.4.3 Jumps .............................................................................................................. 59
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3.4.4 Instruction Cycles and Lengths ................................................................................. 60
3.4.5 Instruction Set Description ...................................................................................... 62
3.4.6 Instruction Set Details ............................................................................................ 64
4 CPUX .............................................................................................................................. 115
4.1 CPU Introduction ......................................................................................................... 116
4.2 Interrupts .................................................................................................................. 118
4.3 CPU Registers ............................................................................................................ 119
4.3.1 Program Counter (PC) ......................................................................................... 119
4.3.2 Stack Pointer (SP) .............................................................................................. 119
4.3.3 Status Register (SR) ............................................................................................ 121
4.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 122
4.3.5 General-Purpose Registers (R4 to R15) ..................................................................... 123
4.4 Addressing Modes ....................................................................................................... 125
4.4.1 Register Mode ................................................................................................... 126
4.4.2 Indexed Mode ................................................................................................... 127
4.4.3 Symbolic Mode .................................................................................................. 131
4.4.4 Absolute Mode .................................................................................................. 136
4.4.5 Indirect Register Mode ......................................................................................... 138
4.4.6 Indirect Autoincrement Mode .................................................................................. 139
4.4.7 Immediate Mode ................................................................................................ 140
4.5 MSP430 and MSP430X Instructions .................................................................................. 142
4.5.1 MSP430 Instructions ............................................................................................ 142
4.5.2 MSP430X Extended Instructions .............................................................................. 147
4.6 Instruction Set Description .............................................................................................. 160
4.6.1 Extended Instruction Binary Descriptions .................................................................... 161
4.6.2 MSP430 Instructions ............................................................................................ 163
4.6.3 MSP430X Extended Instructions .............................................................................. 215
4.6.4 MSP430X Address Instructions ............................................................................... 257
5 Basic Clock Module+ ........................................................................................................ 272
5.1 Basic Clock Module+ Introduction ..................................................................................... 273
5.2 Basic Clock Module+ Operation ....................................................................................... 275
5.2.1 Basic Clock Module+ Features for Low-Power Applications .............................................. 276
5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 276
5.2.3 LFXT1 Oscillator ................................................................................................ 276
5.2.4 XT2 Oscillator ................................................................................................... 277
5.2.5 Digitally-Controlled Oscillator (DCO) ......................................................................... 277
5.2.6 DCO Modulator .................................................................................................. 279
5.2.7 Basic Clock Module+ Fail-Safe Operation ................................................................... 279
5.2.8 Synchronization of Clock Signals ............................................................................. 280
5.3 Basic Clock Module+ Registers ........................................................................................ 282
5.3.1 DCOCTL, DCO Control Register ............................................................................. 283
5.3.2 BCSCTL1, Basic Clock System Control Register 1 ........................................................ 283
5.3.3 BCSCTL2, Basic Clock System Control Register 2 ........................................................ 284
5.3.4 BCSCTL3, Basic Clock System Control Register 3 ........................................................ 285
5.3.5 IE1, Interrupt Enable Register 1 .............................................................................. 286
5.3.6 IFG1, Interrupt Flag Register 1 ................................................................................ 286
6 DMA Controller ................................................................................................................ 287
6.1 DMA Introduction ......................................................................................................... 288
6.2 DMA Operation ........................................................................................................... 290
6.2.1 DMA Addressing Modes ....................................................................................... 290
6.2.2 DMA Transfer Modes ........................................................................................... 291
6.2.3 Initiating DMA Transfers ....................................................................................... 297
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6.2.4 Stopping DMA Transfers ....................................................................................... 298
6.2.5 DMA Channel Priorities ........................................................................................ 299
6.2.6 DMA Transfer Cycle Time ..................................................................................... 299
6.2.7 Using DMA With System Interrupts ........................................................................... 299
6.2.8 DMA Controller Interrupts ...................................................................................... 300
6.2.9 Using the USCI_B I
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C Module with the DMA Controller ................................................... 300
6.2.10 Using ADC12 with the DMA Controller ...................................................................... 301
6.2.11 Using DAC12 With the DMA Controller ..................................................................... 301
6.2.12 Writing to Flash With the DMA Controller .................................................................. 301
6.3 DMA Registers ........................................................................................................... 302
6.3.1 DMACTL0, DMA Control Register 0 .......................................................................... 303
6.3.2 DMACTL1, DMA Control Register 1 .......................................................................... 303
6.3.3 DMAxCTL, DMA Channel x Control Register ............................................................... 304
6.3.4 DMAxSA, DMA Source Address Register ................................................................... 305
6.3.5 DMAxDA, DMA Destination Address Register .............................................................. 306
6.3.6 DMAxSZ, DMA Size Address Register ....................................................................... 306
6.3.7 DMAIV, DMA Interrupt Vector Register ...................................................................... 307
7 Flash Memory Controller .................................................................................................. 308
7.1 Flash Memory Introduction ............................................................................................. 309
7.2 Flash Memory Segmentation ........................................................................................... 309
7.2.1 SegmentA ........................................................................................................ 310
7.3 Flash Memory Operation ................................................................................................ 311
7.3.1 Flash Memory Timing Generator ............................................................................. 311
7.3.2 Erasing Flash Memory ......................................................................................... 312
7.3.3 Writing Flash Memory .......................................................................................... 315
7.3.4 Flash Memory Access During Write or Erase ............................................................... 320
7.3.5 Stopping a Write or Erase Cycle .............................................................................. 321
7.3.6 Marginal Read Mode ........................................................................................... 321
7.3.7 Configuring and Accessing the Flash Memory Controller ................................................. 321
7.3.8 Flash Memory Controller Interrupts ........................................................................... 321
7.3.9 Programming Flash Memory Devices ........................................................................ 321
7.4 Flash Memory Registers ................................................................................................ 323
7.4.1 FCTL1, Flash Memory Control Register ..................................................................... 324
7.4.2 FCTL2, Flash Memory Control Register ..................................................................... 324
7.4.3 FCTL3, Flash Memory Control Register ..................................................................... 325
7.4.4 FCTL4, Flash Memory Control Register ..................................................................... 326
7.4.5 IE1, Interrupt Enable Register 1 .............................................................................. 326
8 Digital I/O ........................................................................................................................ 327
8.1 Digital I/O Introduction ................................................................................................... 328
8.2 Digital I/O Operation ..................................................................................................... 328
8.2.1 Input Register PxIN ............................................................................................. 328
8.2.2 Output Registers PxOUT ....................................................................................... 328
8.2.3 Direction Registers PxDIR ..................................................................................... 329
8.2.4 Pullup/Pulldown Resistor Enable Registers PxREN ........................................................ 329
8.2.5 Function Select Registers PxSEL and PxSEL2 ............................................................. 329
8.2.6 Pin Oscillator ..................................................................................................... 330
8.2.7 P1 and P2 Interrupts ............................................................................................ 331
8.2.8 Configuring Unused Port Pins ................................................................................. 332
8.3 Digital I/O Registers ..................................................................................................... 333
9 Supply Voltage Supervisor (SVS) ....................................................................................... 335
9.1 Supply Voltage Supervisor (SVS) Introduction ....................................................................... 336
9.2 SVS Operation ........................................................................................................... 337
9.2.1 Configuring the SVS ............................................................................................ 337
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9.2.2 SVS Comparator Operation ................................................................................... 337
9.2.3 Changing the VLDx Bits ........................................................................................ 337
9.2.4 SVS Operating Range .......................................................................................... 338
9.3 SVS Registers ............................................................................................................ 339
9.3.1 SVSCTL, SVS Control Register ............................................................................... 340
10 Watchdog Timer+ (WDT+) ................................................................................................. 341
10.1 Watchdog Timer+ (WDT+) Introduction ............................................................................... 342
10.2 Watchdog Timer+ Operation ........................................................................................... 344
10.2.1 Watchdog Timer+ Counter .................................................................................... 344
10.2.2 Watchdog Mode ................................................................................................ 344
10.2.3 Interval Timer Mode ........................................................................................... 344
10.2.4 Watchdog Timer+ Interrupts .................................................................................. 344
10.2.5 Watchdog Timer+ Clock Fail-Safe Operation .............................................................. 345
10.2.6 Operation in Low-Power Modes ............................................................................. 345
10.2.7 Software Examples ............................................................................................ 345
10.3 Watchdog Timer+ Registers ............................................................................................ 346
10.3.1 WDTCTL, Watchdog Timer+ Register ...................................................................... 347
10.3.2 IE1, Interrupt Enable Register 1 ............................................................................. 348
10.3.3 IFG1, Interrupt Flag Register 1 ............................................................................... 348
11 Hardware Multiplier .......................................................................................................... 349
11.1 Hardware Multiplier Introduction ....................................................................................... 350
11.2 Hardware Multiplier Operation .......................................................................................... 350
11.2.1 Operand Registers ............................................................................................. 351
11.2.2 Result Registers ................................................................................................ 351
11.2.3 Software Examples ............................................................................................ 352
11.2.4 Indirect Addressing of RESLO ............................................................................... 353
11.2.5 Using Interrupts ................................................................................................ 353
11.3 Hardware Multiplier Registers .......................................................................................... 354
12 Timer_A .......................................................................................................................... 355
12.1 Timer_A Introduction .................................................................................................... 356
12.2 Timer_A Operation ....................................................................................................... 357
12.2.1 16-Bit Timer Counter .......................................................................................... 357
12.2.2 Starting the Timer .............................................................................................. 358
12.2.3 Timer Mode Control ........................................................................................... 358
12.2.4 Capture/Compare Blocks ..................................................................................... 362
12.2.5 Output Unit ...................................................................................................... 363
12.2.6 Timer_A Interrupts ............................................................................................. 367
12.3 Timer_A Registers ....................................................................................................... 369
12.3.1 TACTL, Timer_A Control Register ........................................................................... 370
12.3.2 TAR, Timer_A Register ....................................................................................... 371
12.3.3 TACCRx, Timer_A Capture/Compare Register x .......................................................... 371
12.3.4 TACCTLx, Capture/Compare Control Register ............................................................ 372
12.3.5 TAIV, Timer_A Interrupt Vector Register ................................................................... 373
13 Timer_B .......................................................................................................................... 374
13.1 Timer_B Introduction .................................................................................................... 375
13.1.1 Similarities and Differences From Timer_A ................................................................ 375
13.2 Timer_B Operation ....................................................................................................... 377
13.2.1 16-Bit Timer Counter .......................................................................................... 377
13.2.2 Starting the Timer .............................................................................................. 377
13.2.3 Timer Mode Control ........................................................................................... 377
13.2.4 Capture/Compare Blocks ..................................................................................... 381
13.2.5 Output Unit ...................................................................................................... 384
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SLAU144J–December 2004–Revised July 2013 Contents
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Copyright © 2004–2013, Texas Instruments Incorporated
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