8.6.1 Minimum Flash Specification ................................................................................................. 36
8.6.2 Common Flash Interface ........................................................................................................ 36
8.6.3 Virtual Machine Requirements ............................................................................................... 37
8.6.4 Memory Timing ...................................................................................................................... 38
9 Serial Interfaces ............................................................................................................................................ 40
9.1 UART Interface .................................................................................................................................... 40
9.1.1 UART Configuration While Reset is Active ............................................................................ 41
9.1.2 UART Bypass Mode ............................................................................................................... 42
9.1.3 Current Consumption in UART Bypass Mode ........................................................................ 42
9.2 USB Interface ...................................................................................................................................... 42
9.3 Programming and Debug Interface ...................................................................................................... 43
9.3.1 Instruction Cycle ..................................................................................................................... 43
9.3.2 Multi-slave Operation ............................................................................................................. 43
9.4 I²C Interface ......................................................................................................................................... 43
9.4.1 Software I²C Interface ............................................................................................................ 43
9.4.2 Bit-serialiser Interface ............................................................................................................ 44
10 Audio Interface .............................................................................................................................................. 45
10.1 Audio Input and Output ........................................................................................................................ 45
10.2 Stereo Audio Codec Interface .............................................................................................................. 45
10.2.1 Stereo Audio Codec Block Diagram ....................................................................................... 46
10.2.2 Stereo Codec Set-up .............................................................................................................. 46
10.2.3 ADC ........................................................................................................................................ 47
10.2.4 ADC Sample Rate Selection .................................................................................................. 47
10.2.5 ADC Digital Gain .................................................................................................................... 47
10.2.6 ADC Analogue Gain ............................................................................................................... 47
10.2.7 DAC ........................................................................................................................................ 48
10.2.8 DAC Sample Rate Selection .................................................................................................. 48
10.2.9 DAC Digital Gain .................................................................................................................... 48
10.2.10 DAC Analogue Gain ............................................................................................................... 49
10.2.11 IEC 60958 Interface ............................................................................................................... 49
10.2.12 Microphone Input ................................................................................................................... 50
10.2.13 Line Input ............................................................................................................................... 53
10.2.14 Output Stage .......................................................................................................................... 54
10.2.15 Mono Operation ..................................................................................................................... 55
10.2.16 Side Tone ............................................................................................................................... 55
10.2.17 Integrated Digital Filter ........................................................................................................... 55
10.3 PCM Interface ...................................................................................................................................... 56
10.3.1 PCM Interface Master/Slave .................................................................................................. 56
10.3.2 Long Frame Sync ................................................................................................................... 57
10.3.3 Short Frame Sync .................................................................................................................. 57
10.3.4 Multi-slot Operation ................................................................................................................ 58
10.3.5 GCI Interface .......................................................................................................................... 58
10.3.6 Slots and Sample Formats ..................................................................................................... 59
10.3.7 Additional Features ................................................................................................................ 59
10.3.8 PCM Timing Information ........................................................................................................ 60
10.3.9 PCM_CLK and PCM_SYNC Generation ................................................................................ 63
10.3.10 PCM Configuration ................................................................................................................. 63
10.4 Digital Audio Interface (I²S) .................................................................................................................. 65
11 Power Control and Regulation ...................................................................................................................... 70
11.1 Power Sequencing ............................................................................................................................... 70
11.2 External Voltage Source ...................................................................................................................... 71
11.3 Switch-mode Regulator ....................................................................................................................... 71
11.4 High-voltage Linear Regulator ............................................................................................................. 71
11.5 Low-voltage Linear Regulator .............................................................................................................. 71
Contents
CS-121064-DSP4
Production Information
This material is subject to CSR's non-disclosure agreement
© Cambridge Silicon Radio Limited 2006 - 2010
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