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DSMT7620_V.1.3_091212 Page 1 of 54
MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
MT7620
DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
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DSMT7620_V.1.3_091212 Page 2 of 54
MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Applications:
Routers
NAS devices
iNICs
Dual band
concurrent routers
Overview
The MT7620 router-on-a-chip includes an 802.11n MAC and baseband, a 2.4 GHz
radio and FEM, a 580 MHz MIPS® 24K™ CPU core, a 5-port 10/100 switch and two
RGMII. The MT7620 includes everything needed to build an AP router from a
single chip. The embedded high performance CPU can process advanced
applications effortlessly, such as routing, security and VoIP. The MT7620 also
includes a selection of interfaces to support a variety of applications, such as a
USB port for accessing external storage.
Features
Embedded MIPS24KEc (580 MHz) with 64 KB I-
Cache and 32 KB D-Cache
2T2R 2.4 GHz with 300 Mbps PHY data rate
Legacy 802.11b/g and HT 802.11n modes
20/40 MHz channel bandwidth
Legacy 802.11b/g and HT 802.11n modes
Reverse Data Grant (RDG)
Maximal Ratio Combining (MRC)
Space Time Block Coding (STBC)
16-bit SDRAM up to 64 Mbytes
16-bit DDR1/2 up to 128/256 Mbytes (MT7620A)
SPI, NAND Flash/SD-XC
1x USB 2.0, 1x PCIe host/device
5-port 10/100 SW and two RGMII
An optimized PMU
Green AP
Intelligent Clock Scaling (exclusive)
DDRII: ODT off, Self-refresh mode
SDRAM: Pre-charge power down
I2C, I2S, SPI, PCM, UART, JTAG, MDC, MDIO, GPIO
Hardware NAT with IPv6 and 2 Gbps wired speed
16 Multiple BSSID
WEP64/128, TKIP, AES, WPA, WPA2, WAPI
QoS: WMM, WMM-PS
WPS: PBC, PIN
Voice Enterprise: 802.11k+r
AP Firmware: Linux 2.6 SDK, eCOS with IPv6
RGMII iNIC Driver: Linux 2.4/2.6
Functional Block Diagram
MIPS 24KEc
64 KB I-Cache
32 KB D-Cache
(580 MHz)
OCP Bridge
OCP_IF
Arbiter
DRAM
Controller
RBUS (SYS_CLK)
SPI
NFC
PBUS
GDMA
RJ45 x5
Switch
(4FE + 2GE)
5-Port EPHY
RGMII
TMII/MII x2
PCIe 1.1
PHY
Single Port
USB 2.0 PHY
Host/Device
PCIe x1
UART
GPIO
PCM x4
I2S
I2C
I2S
PBUS
INTC
I2C
GPIO
/LED
SPI
NAND
UART
To CPU
interrupts
16-Bit SDR/DDR1/DDR2
EJTAG
WLAN
11n 2x2
2.4 GHz
Timer
PCM
SDHC
SD
Ordering Information
Ralink Technology Corp. (USA)
Suite 200
20833 Stevens Creek Blvd.
Cupertino CA95014, U.S.A
Tel: 408-725-8070
Fax: 408-725-8069
Ralink Technology Corp. (Taiwan)
5F, 5 Taiyuan 1
st
St
Jhubei City, Hsinchu
Taiwan, R.O.C
Tel: 886-3-560-0868
Fax: 886-3-560
www.ralinktech.com
Part
Number
Package
(Green/RoHS Compliant)
MT7620A TFBGA 265 ball
(11 mm x 11 mm)
MT7620N DR-QFN 148 pin
(12 mm x 12 mm)
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DSMT7620_V.1.3_091212 Page 3 of 54
MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Table of Contents
1. MAIN FEATURES 6
2. PINS 7
2.1 TFBGA (11 MM X 11 MM) 265 BALL PACKAGE DIAGRAM 7
2.1.1 DDR2 BALL MAP 7
2.2 DR-QFN (12 MM X 12 MM) 148-PIN PACKAGE DIAGRAM 8
2.2.1 LEFT SIDE VIEW 8
2.2.2 RIGHT SIDE VIEW 9
2.3 PIN DESCRIPTIONS (TFBGA) 11
2.4 PIN DESCRIPTIONS (DRQFN) 17
2.5 PIN SHARING SCHEMES 22
2.5.1 GPIO PIN SHARE SCHEME 22
2.5.2 UARTF PIN SHARE SCHEME 24
2.5.3 RGMII PIN SHARE SCHEMES 25
2.5.4 WDT_RST_MODE PIN SHARE SCHEME 25
2.5.5 PERST_N PIN SHARE SCHEME 25
2.5.6 MDC/MDIO PIN SHARE SCHEME: 25
2.5.7 EPHY_LED PIN SHARE SCHEME 26
2.5.8 SPI PIN SHARE SCHEME 26
2.5.9 ND/SD PIN SHARE SCHEME 27
2.5.10 XMII PHY/MAC PIN MAPPING 29
2.6 BOOTSTRAPPING PINS DESCRIPTION 30
3. MAXIMUM RATINGS AND OPERATING CONDITIONS 31
3.3 ABSOLUTE MAXIMUM RATINGS 31
3.4 MAXIMUM TEMPERATURES 31
3.5 OPERATING CONDITIONS 31
3.6 THERMAL CHARACTERISTICS 31
3.7 STORAGE CONDITIONS 32
3.8 EXTERNAL XTAL SPECFICATION 32
3.9 DC ELECTRICAL CHARACTERISTICS 32
3.10 AC ELECTRICAL CHARACTERISTICS 33
3.10.1 SDRAM INTERFACE 33
3.10.2 DDR2 SDRAM INTERFACE 34
3.10.3 RGMII INTERFACE 36
3.10.4 MII INTERFACE (25 MHZ) 37
3.10.5 RVMII INTERFACE (PHY MODE MII TIMING) (25 MHZ) 38
3.10.6 SPI INTERFACE 39
3.10.7 I
2
S INTERFACE 40
3.10.8 PCM INTERFACE 41
3.10.9 POWER ON SEQUENCE 42
3.11 PACKAGE PHYSICAL DIMENSIONS 43
3.11.1 TFBGA (11 MM X 11 MM) 265 BALLS 43
3.11.2 DR-QFN (12 MM X 12 MM) 148LD 45
3.11.3 MT7620 N/A MARKING 48
3.11.4 REFLOW PROFILE GUIDELINE 49
4. ABBREVIATIONS 50
5. REVISION HISTORY 53
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DSMT7620_V.1.3_091212 Page 4 of 54
MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
Table of Figures
FIGURE 2-1 DR-QFN PIN DIAGRAM (LEFT VIEW) .............................................................................................................. 9
FIGURE 2-2 DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW) ................................................................................................... 10
FIGURE 2-3 MII MII PHY ..................................................................................................................................... 29
FIGURE 2-4 RVMII MII MAC ................................................................................................................................ 29
FIGURE 2-5 RGMII RGMII PHY ............................................................................................................................. 29
FIGURE 2-6 RGMII RGMII MAC ........................................................................................................................... 29
FIGURE 3-1 SDRAM INTERFACE .................................................................................................................................. 33
FIGURE 3-2 DDR2 SDRAM COMMAND ....................................................................................................................... 34
FIGURE 3-3 DDR2 SDRAM WRITE DATA ...................................................................................................................... 34
FIGURE 3-4 DDR2 SDRAM READ DATA ....................................................................................................................... 34
FIGURE 3-5 RGMII INTERFACE .................................................................................................................................... 36
FIGURE 3-6 MII INTERFACE ......................................................................................................................................... 37
FIGURE 3-7 RVMII INTERFACE ..................................................................................................................................... 38
FIGURE 3-8 SPI INTERFACE ......................................................................................................................................... 39
FIGURE 3-9 I2S INTERFACE ......................................................................................................................................... 40
FIGURE 3-10 PCM INTERFACE ..................................................................................................................................... 41
FIGURE 3-11 POWER ON SEQUENCE ............................................................................................................................ 42
FIGURE 3-12 TFBGA TOP VIEW .................................................................................................................................. 43
FIGURE 3-13 TFBGA SIDE VIEW .................................................................................................................................. 43
FIGURE 3-14 TFBGA “A” EXPANDED ........................................................................................................................... 43
FIGURE 3-15 TFBGA BOTTOM VIEW ............................................................................................................................ 44
FIGURE 3-16 TFBGA “B” EXPANDED ........................................................................................................................... 44
FIGURE 3-17 DR-QFN TOP VIEW ................................................................................................................................ 45
FIGURE 3-18 DR-QFN SIDE VIEW ............................................................................................................................... 45
FIGURE 3-19 DR-QFN “B” EXPANDED ......................................................................................................................... 45
FIGURE 3-20 DR-QFN BOTTOM VIEW ......................................................................................................................... 46
FIGURE 3-21 DR-QFN “A” EXPANDED ......................................................................................................................... 46
FIGURE 3-22 MT7620N TOP MARKING ........................................................................................................................ 48
FIGURE 3-23 MT7620A TOP MARKING ........................................................................................................................ 48
FIGURE 3-24 REFLOW PROFILE FOR MT7620 ................................................................................................................ 49
List of Tables
TABLE 1-1 MAIN FEATURES ........................................................................................................................................... 6
TABLE 2-1 DDR2 BALL MAP ......................................................................................................................................... 8
TABLE 3-1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 31
TABLE 3-2 MAXIMUM TEMPERATURES .......................................................................................................................... 31
TABLE 3-3 OPERATING CONDITIONS ............................................................................................................................. 31
TABLE 3-4 THERMAL CHARACTERISTICS ......................................................................................................................... 31
TABLE 3-5 EXTERNAL XTAL SPECIFICATIONS .................................................................................................................... 32
TABLE 3-6 DC ELECTRICAL CHARACTERISTICS .................................................................................................................. 32
TABLE 3-7 VDD 2.5V ELECTRICAL CHARACTERISTICS ........................................................................................................ 32
TABLE 3-8 SDRAM INTERFACE DIAGRAM KEY ................................................................................................................ 33
TABLE 3-9 DDR2 SDRAM INTERFACE DIAGRAM KEY ...................................................................................................... 35
TABLE 3-10 RGMII INTERFACE DIAGRAM KEY ................................................................................................................ 36
TABLE 3-11 MII INTERFACE DIAGRAM KEY .................................................................................................................... 37
TABLE 3-12 RVMII INTERFACE DIAGRAM KEY ................................................................................................................ 38
TABLE 3-13 SPI INTERFACE DIAGRAM KEY ..................................................................................................................... 39
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DSMT7620_V.1.3_091212 Page 5 of 54
MT7620 DATASHEET
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
TABLE 3-14 I2S INTERFACE DIAGRAM KEY ..................................................................................................................... 40
TABLE 3-15 PCM INTERFACE DIAGRAM KEY .................................................................................................................. 41
TABLE 3-16 POWER ON SEQUENCE DIAGRAM KEY .......................................................................................................... 42
