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88E6320_DB_QFN108_REV2 1.pdf
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88E6320_DB
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
12-13
14
17-18 Power supply
Page No.
Table of Contents
Description
2
3
4
5
Top level block diagram
88E6320 Chip Interface
88E6320 Configuration
RESET & GPHY LED's
6-7
11
P5 RGMII I/F
P2 RGMII I/F
9-10
8
15-16
P0-P1 Serdes to Fiber
Designer : Amulya K Patra
88E6320/21 DB Board
SMI USB/CPLD I/F
P3-P4 GPHY
P2 MDI I/F
P6 RGMII I/F
REV 2.1 HISTORY:
1. Regulators replaced to support 5V and 12V Input
2. POR Chip Added on Board
3. MAGJACK on all ports made same
4. Series termination Resistor replaced with 0 Ohm on External PHY
5. V_Set reistor values corrected for 88PH485
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
1 18Wednesday, January 22, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
1 18Wednesday, January 22, 2014
Title
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Date: Sheet of
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88E6320/21 DB Schematics
Custom
1 18Wednesday, January 22, 2014
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Pearl DB
PORT-0 PORT-1 PORT-2 PORT-3
POWER RESET EEPROM CLOCK
PORT-6
PORT-5
PORT-5 CONFIG
PORT-6 CONFIG
TOP LEVEL BLOCK DIAGRAM
SMI MDC/MDIO
Integrated
Magnetics RJ45
Copper Port
10/100/1000 Mbps
E1116R PHY
RGMII
SFP
Serdes
SFP
Serdes
E1116R
RGMII
Integrated
Magnetics RJ45
Copper Port
10/100/1000 Mbps
GPHY
Integrated
Magnetics RJ45
Copper Port
10/100/1000 Mbps
GPHY
PORT-4
Integrated
Magnetics RJ45
Copper Port
10/100/1000 Mbps
RGMII
E1116R PHY
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
2 18Wednesday, January 22, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
2 18Wednesday, January 22, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
2 18Wednesday, January 22, 2014
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
88E6320 Chip
P5 I/O SEL
------------
0X:1.8V
10: 3.3V
11: 2.5V
P6 I/O SEL
------------
0X:1.8V
10: 3.3V
11: 2.5V
VDD_CORE
VOUT11
VDD33_IN
VOUT15
P5_VDDOS[0]
NO_CPU
LED_SEL1
LED_SEL0
ADDR1n
ADDR0n
ADDR2n
ADDR3n
ADDR4n
VDD33_IN
P6_VDDOS[0]
P0_SMODE
P1_SMODE
VDD_15
VDD_15
VDD_15
VDD_15
ADDR1n
ADDR2n
P5_VDDOS[0]
P6_VDDOS[0]
VDD33_PLL
VOUT15
VDD_CORE
EE_DOUT
FLOW
VDD33_PLL
NO_CPU
LED_SEL0
LED_SEL1
EEE_WP
P0_SMODE
P1_SMODE
VOUT15
ADDR3n
ADDR4n
VOUT11
ADDR0n
EEE_WP
P0_SMODE
P1_SMODE
FLOW
MDIO_PHY 4
MDIO_CPU
15
VDD_2.5V
VDD_2.5V
VDD_2.5V
VDD_2.5V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_2.5V
VDD_2.5V
VDD_3.3V
VDD_3.3V
VDD_2.5V
VDD_3.3V
VDD_3.3V
VDD_3.3V
P3_MDIN_312
P3_MDIP_312
P3_MDIN_212
P3_MDIP_212
P3_MDIN_112
P3_MDIP_112
P3_MDIN_012
P3_MDIP_012
P4_MDIN_013
P4_MDIP_013
P4_MDIP_113
P4_MDIN_113
P4_MDIP_213
P4_MDIN_213
P4_MDIP_313
P4_MDIN_313
P5_IND3
6
P5_IND2
6
P5_IND1
6
P5_IND0
6
P5_INDV
6
P5_INCLK
6
P5_OUTCLK
6
P5_OUTEN
6
P5_OUTD1
6
P5_OUTD2
6
P5_OUTD3
6
XTAL_OUT
4
XTAL_IN
4
EE_DOUT_C1_LED_P4_LED0
4,5
EE_CLK_C0_LED_FLOW
4,5
R2_LED_P3_LED0_NO_CPU5
R1_LED_P1_LED0_LED_SEL15
R0_LED_P0_LED0_LED_SEL0
5
SW_RESETn
4
P2_OUTD0
11
P2_TXC11
P2_RXC
11
P2_INDV11
P2_IND0
11
P2_IND1
11
P2_IND2
11
P2_IND3
11
P0_S_TXP
8
P0_S_TXN
8
P0_S_RXP
8
P0_S_RXN
8
P1_S_TXP8
P1_S_TXN8
P1_S_RXP
8
P1_S_RXN8
P2_OUTD1
11
P2_OUTD2
11
P2_OUTD3
11
P6_IND0
9
P6_IND1
9
P6_IND2
9
P6_IND3
9
P6_INDV
9
P6_INCLK
9
P6_OUTCLK
9
P6_OUTEN
9
P6_OUTD0
9
P6_OUTD1
9
P6_OUTD2
9
P6_OUTD3
9
MDC_PHY
4
P2_OUTEN11
MDC_CPU
15
P5_OUTD0
6
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
3 18Wednesday, January 22, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
3 18Wednesday, January 22, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
3 18Wednesday, January 22, 2014
C278
0.1uF
C1034
10uF_6.3V
R19 0
R991 4.7K
R996 4.7K
SW11
SW8_DIP16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R861 150
R973 22.1
R970 22.1
J13
SMA_TH_UP
R986 4.7K_NOB
C279
0.1uF
R965 22.1
R17
0
R920 4.7K
R20
0
D56
LED_GREEN
R8 0
R987 4.7K_NOB
C313
0.1uF
C280
0.1uF
C25
10uF_6.3V
R48
0
R949
4.7K
R974 22.1
R968 22.1
C281
0.1uF
C285
0.1uF
C1036
10uF_6.3V
R134
0
C20
10uF_6.3V
R997 4.7K_NOB
R976 22.1
R971 22.1
C325
0.1uF
C2468nF
88E6320
88E6320F_QFN108
P5_VDDO
40
XTAL_OUT
35
P5_CRS/MDC_PHY/GPIO[8]
53
P5_COL/MDIO_PHY/GPIO[7]
52
MDC_CPU
55
MDIO_CPU
54
P5_VDDO
47
XTAL_IN
34
NC/TSTPT
31
NC/HSDAC_P
30
VDD_CORE
38
INTn
56
VDD33_PLL
57
P6_OUTCLK/P6_TXC
75
P6_VDDO
74
GPIO[3]/P0_SMODE
68
VSS/TEST
66
P6_VDDO
82
P6_OUTD[0]/P6_MODE[0]
72
VOUT11
63
P6_OUTD[2]/P6_MODE[2]
70
P6_OUTD[3]/P6_VDDOS[1]
69
VDD33
58
P6_IND[2]
80
P6_IND[1]
79
P6_OUTEN/P6_VDDOS[0]
73
VDD_CORE
65
VOUT15_SEN
61
EE_DOUT/C1_LED/P4_LED0
97
P6_CRS/P2_INDV/GPIO[10]
91
P6_IND[4]/P2_IND[0]/GPIO[11]
92
P6_OUTD[7]/P2_OUTD[3]/ADDR[4]n
83
P6_OUTD[5]/P2_OUTD[1]/ADDR[2]n
85
P0_S_RXN
108
VDD_CORE
96
P6_IND[7]/P2_IND[3]/GPIO[14]
95
P6_IND[6]/P2_IND[2]/GPIO[13]
94
P6_IND[5]/P2_IND[1]/GPIO[12]
93
P6_OUTD[6]/P2_OUTD[2]/ADDR[3]n
84
VOUT11_SEN
62
P3_MDIN[0]
8
P3_MDIP[0]
7
P3_MDIP[2]
13
P3_MDIN[2]
14
P3_MDIP[3]
15
P3_MDIN[3]
16
VSS
6
NC/SE_SCLK
32
EE_CLK/C0_LED/FLOW
98
EE_VDDO
99
RESETn
103
R1_LED/P1_LED0/LED_SEL[1]
101
R0_LED/P0_LED0/LED_SEL[0]
102
P0_S_TXP
104
P0_S_TXN
105
P0_AVDD15
106
P0_S_RXP
107
R2_LED/P3_LED0/NO_CPU
100
P6_COL/P2_INCLK/GPIO[9]
90
P6_OUTD[4]/P2_OUTD[0]/ADDR[1]n
86
P2_OUTEN/EEE_WP
87
P6_GTXCLK/P2_TXC/ADDR[0]n
88
P6_VDDO
89
P6_INCLK
76
P6_INDV
77
P6_IND[0]
78
P6_IND[3]
81
P6_OUTD[1]/P6_MODE[1]
71
GPIO[4]/P1_SMODE
67
CBOT
64
VOUT15
60
CTOP
59
P5_IND[3]/GPIO[6]
51
P5_IND[2]/GPIO[5]
50
P5_IND[1]
49
P5_IND[0]
48
P5_INDV/GPIO[2]
46
P5_INCLK/GPIO[1]
45
P5_OUTCLK/P5_TXC/GPIO[0]
44
P5_OUTEN/P5_VDDOS[0]
43
P5_OUTD[0]/P5_MODE[0]
42
P5_OUTD[1]/P5_MODE[1]
41
P5_OUTD[2]/P5_MODE[2]
39
P5_OUTD[3]/P5_VDDOS[1]
37
XTAL_GND
36
AVDD15
33
NC/HSDAC_N
29
RSET
28
P1_S_TXP
1
P1_S_TXN
2
P1_AVDD15
3
P1_S_RXP
4
P1_S_RXN
5
P3_AVDD15
9
P3_MDIP[1]
10
P3_MDIN[1]
11
P3_AVDD33
12
P4_MDIP[0]
17
P4_MDIN[0]
18
P4_AVDD15
19
P4_MDIP[1]
20
P4_MDIN[1]
21
P4_AVDD33
22
P4_MDIP[2]
23
P4_MDIN[2]
24
P4_MDIP[3]
25
P4_MDIN[3]
26
AVDD15
27
epad
109
C310
0.1uF
C315
0.1uF
TP34
Header_1x1
C284
0.1uF
J14
SMA_TH_UP
C26
10uF_6.3V
C307
0.1uF
C1038
10uF_6.3V
C314
0.1uF
C311
0.1uF
C308
0.1uF
R967 22.1
R977 22.1
C1035
10uF_6.3V
C27
10uF_6.3V
R964 22.1
R969 22.1
C301
0.1uF
R966 22.1
R988 4.7K_NOB
TP32
Header_1x1
R972 22.1
C302
0.1uF
C318
0.1uF
C309
0.1uF
R59
0
R975 22.1
C282
0.1uF
R1005 22
R945
4.7K
TP33
Header_1x1
C36
10uF_6.3V
JP69
Header_1x2
12
C283
0.1uF
R865
4.99K
R898
1.5K
C1032
10uF_6.3V
C12
10uF_6.3V
R992 4.7K
R990 4.7K_NOB
J12
SMA_TH_UP
C276
0.1uF
C19
10uF_6.3V
R978 22.1
C305
0.1uF
R995 4.7K
C312
0.1uF
C277
0.1uF
R919 4.7K
R994 4.7K
C322
0.1uF
C1037
10uF_6.3V
C306
0.1uF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
2-WIRE EEPROM
System Reset
88E6320 Clk & MDC/MDIO
MDIO_PHY 3
P5_E1116_MDIO
11,6,9
P2_E1116_MDIO
11,6,9
P6_E1116_MDIO
11,6,9
VDD_3.3V
VDD_2.5V
VDD_3.3V
VDD_2.5V
VDD_3.3V
XTAL_IN
3
XTAL_OUT
3
MDC_PHY 3
P5_E1116_MDC
6
P2_E1116_MDC
E1116_RESETn
11,6,9
SW_RESETn
3
EE_DOUT_C1_LED_P4_LED0
3,5
EE_CLK_C0_LED_FLOW
3,5
P6_E1116_MDC
9
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
4 18Wednesday, January 22, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
4 18Wednesday, January 22, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> -
88E6320/21 DB Schematics
Custom
4 18Wednesday, January 22, 2014
R12 0
R14 0
R129
33
C273
0.1uF
R128 33
C272
0.1uF
R13 0
C5
470pF
R11 0
SW7
SW_PUSHBUTTON
R621
49.9_NOB
C6
27pF
C274
0.1uF
R116
1K
C826
47pF
J18
SMA_TH_UP
U63
NC7WZ126
OE1
1
A1
2
GND0
4
Y1
6
VCC0
8
A2
5
Y2
3
OE2
7
C825
47pF
R121 33
C59
10uF_6.3V
U64
NC7WZ126
OE1
1
A1
2
GND0
4
Y1
6
VCC0
8
A2
5
Y2
3
OE2
7
C8
27pF
J19
SMA_TH_UP
C60
0.1uF
R931 4.7K
R122 33
R625
49.9_NOB R620
49.9_NOB
Y2
CRYSTAL_25MHz
U4
S24CS04A
A0
1
A1
2
A2
3
GND
4
VCC
8
WP
7
SCL
6
SDA
5
U3 MXD1818UR22-T
RESET
1
VCC
2
GND
3
C824
47pF
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